33 lines
628 B
Verilog
33 lines
628 B
Verilog
// Ensure the compiler doesn't perform some invalid optimisations.
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module test();
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reg [3:0] unknown;
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reg [3:0] result;
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reg failed;
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initial begin
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failed = 0;
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unknown = 4'bx101;
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result = unknown + 0;
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$display("%b", result);
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if (result !== 4'bxxxx) failed = 1;
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result = (unknown >> 1) + 0;
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$display("%b", result);
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if (result !== 4'bxxxx) failed = 1;
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result = unknown - 0;
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$display("%b", result);
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if (result !== 4'bxxxx) failed = 1;
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result = unknown * 0;
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$display("%b", result);
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if (result !== 4'bxxxx) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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