53 lines
1.1 KiB
Verilog
53 lines
1.1 KiB
Verilog
nature Voltage;
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units = "V";
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access = V;
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idt_nature = Flux;
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abstol = 1e-6;
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endnature
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discipline voltage;
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potential Voltage;
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enddiscipline
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nature Flux;
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units = "Wb";
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access = Phi;
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ddt_nature = Voltage;
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abstol = 1e-9;
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endnature
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`timescale 1s/1s
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module main;
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real value;
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voltage in, out;
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analog V(out) <+ transition(value, 0, 4);
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initial begin
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value = 0.0;
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#10 if (V(out) != value) begin
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$display("FAILED -- value=%g, res=%g", value, V(out));
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$finish;
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end
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// Halfway through the rise time, the output should have
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// half the input.
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value = 2.0;
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//#2 if (V(out) != value/2) begin
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#2 if (abs(V(out) - value/2) > 1e-6) begin
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$display("FAILED -- value=%g, value/2=%g, res=%f", value, value/2, V(out));
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$finish;
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end
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// After the full transition time, the output should match
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// the input.
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#2 if (V(out) != value) begin
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$display("FAILED -- value=%g, res=%f", value, V(out));
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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