62 lines
1.4 KiB
Verilog
62 lines
1.4 KiB
Verilog
module top;
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reg a;
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reg q, d;
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event foo;
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real rl;
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int ar [];
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int start = 0;
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int stop = 1;
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int step = 1;
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int done = 0;
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task a_task;
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real trl;
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event tevt;
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reg tvr;
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$display("user task");
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endtask
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always_latch begin: blk_name
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event int1, int2;
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real intrl;
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q = d;
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-> foo;
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rl = 0.0;
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rl <= 1.0;
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ar = new [2];
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for (int idx = start; idx < stop; idx += step) $display("For: %0d", idx);
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for (int idx = 0; done; idx = done + 1) $display("Should never run!");
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for (int idx = 0; idx; done = done + 1) $display("Should never run!");
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for (int idx = 0; idx; {done, idx} = done + 1) $display("Should never run!");
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for (int idx = 0; idx; idx <<= 1) $display("Should never run!");
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for (int idx = 0; idx; idx = idx << 1) $display("Should never run!");
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$display("array size: %0d", ar.size());
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ar.delete();
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$display("array size: %0d", ar.size());
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a_task;
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assign a = 1'b0;
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deassign a;
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do $display("do/while");
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while (a);
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force a = 1'b1;
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release a;
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while(a) begin
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$display("while");
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a = 1'b0;
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end
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repeat(2) $display("repeat");
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disable out_name;
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forever begin
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$display("forever");
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disable blk_name; // This one should not generate a warning
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end
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end
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initial #1 $display("Expect compile warnings!\nPASSED");
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initial begin: out_name
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#2 $display("FAILED");
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end
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endmodule
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