25 lines
402 B
Verilog
25 lines
402 B
Verilog
module top;
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reg a, b;
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reg q, d;
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event foo;
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always_latch begin
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q <= d;
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fork
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$display("fork/join 1");
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join
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fork
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$display("fork/join_any 1");
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join_any
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fork
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$display("fork/join_none 1");
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join_none
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a <= @foo 1'b1;
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@(b) a <= repeat(2) @foo 1'b0;
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wait (!a) $display("wait");
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end
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initial #1 $display("Expect compile errors!");
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endmodule
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