88 lines
1.6 KiB
Verilog
88 lines
1.6 KiB
Verilog
module top;
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reg y, a, b, flip, hidden, en;
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reg pass;
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function f_and (input i1, i2);
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reg partial;
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begin
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partial = i1 & i2;
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f_and = partial | hidden;
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end
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endfunction
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reg intr;
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always_latch begin
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if (en) begin
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intr = flip;
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y <= f_and(a, b) ^ intr;
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end
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end
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initial begin
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pass = 1'b1;
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en = 1'b1;
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flip = 1'b0;
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hidden = 1'b0;
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a = 1'b0;
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b = 1'b0;
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#1;
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if (y !== 1'b0) begin
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$display("FAILED: a=1'b0, b=1'b0, hidden=1'b0, expected 1'b0, got %b", y);
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pass = 1'b0;
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end
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a = 1'b0;
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b = 1'b1;
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#1;
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if (y !== 1'b0) begin
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$display("FAILED: a=1'b0, b=1'b1, hidden=1'b0, expected 1'b0, got %b", y);
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pass = 1'b0;
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end
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a = 1'b1;
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b = 1'b0;
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#1;
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if (y !== 1'b0) begin
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$display("FAILED: a=1'b1, b=1'b0, hidden=1'b0, expected 1'b0, got %b", y);
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pass = 1'b0;
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end
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a = 1'b1;
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b = 1'b1;
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#1;
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if (y !== 1'b1) begin
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$display("FAILED: a=1'b1, b=1'b1, hidden=1'b0, expected 1'b1, got %b", y);
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pass = 1'b0;
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end
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hidden = 1'b0;
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a = 1'b0;
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b = 1'b0;
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#1;
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if (y !== 1'b0) begin
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$display("FAILED: a=1'b0, b=1'b0, hidden=1'b0, expected 1'b0, got %b", y);
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pass = 1'b0;
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end
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hidden = 1'b1;
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a = 1'b0;
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b = 1'b0;
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#1;
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if (y !== 1'b1) begin
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$display("FAILED: a=1'b0, b=1'b0, hidden=1'b1, expected 1'b1, got %b", y);
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pass = 1'b0;
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end
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en = 1'b0;
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hidden = 1'b0;
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#1;
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if (y !== 1'b1) begin
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$display("FAILED: en=1'b0, expected 1'b1, got %b", y);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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