65 lines
1.3 KiB
Verilog
65 lines
1.3 KiB
Verilog
module top;
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reg q1, q2, q3, q4, q5, q6, q7, d;
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reg clk;
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reg [5:4] rst;
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integer i;
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// The compiler should warn that clk is missing an edge keyword.
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always_ff @(clk) begin
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q1 <= d;
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end
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// The compiler should warn that rst is missing an edge keyword.
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always_ff @(posedge clk or rst[4]) begin
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if (rst[4])
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q2 <= 1'b0;
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else
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q2 <= d;
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end
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// The compiler should warn that rst is missing an edge keyword.
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always_ff @(posedge clk or rst[i]) begin
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if (rst[i])
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q3 <= 1'b0;
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else
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q3 <= d;
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end
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// The compiler should warn that rst is missing an edge keyword.
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always_ff @(posedge clk or !rst) begin
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if (!rst)
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q4 <= 1'b0;
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else
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q4 <= d;
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end
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// The compiler should warn that rst is missing an edge keyword.
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always_ff @(posedge clk or ~rst[4]) begin
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if (~rst[4])
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q5 <= 1'b0;
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else
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q5 <= d;
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end
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// The compiler should warn that rst is missing an edge keyword.
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always_ff @(posedge clk or &rst) begin
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if (&rst)
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q6 <= 1'b0;
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else
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q6 <= d;
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end
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// The compiler should warn that rst is not a single bit.
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always_ff @(posedge clk or posedge rst) begin
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if (rst)
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q7 <= 1'b0;
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else
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q7 <= d;
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end
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initial begin
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$display("Expect compile warnings!\nPASSED");
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end
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endmodule
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