44 lines
761 B
Verilog
44 lines
761 B
Verilog
module top;
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reg q, clk, d;
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reg pass;
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always_ff @(posedge clk) begin
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q <= d;
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end
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initial begin
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pass = 1'b1;
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#1;
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if (q !== 1'bx) begin
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$display("FAILED: initally expected 1'bx, got %b", q);
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pass = 1'b0;
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end
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d = 1'b0;
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clk = 1'b1;
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#1;
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if (q !== 1'b0) begin
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$display("FAILED: clock in a 0 expected 1'b0, got %b", q);
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pass = 1'b0;
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end
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d = 1'b1;
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clk = 1'b0;
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#1;
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if (q !== 1'b0) begin
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$display("FAILED: no clock change expected 1'b0, got %b", q);
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pass = 1'b0;
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end
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clk = 1'b1;
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#1;
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if (q !== 1'b1) begin
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$display("FAILED: clock in a 1 expected 1'b1, got %b", q);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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