61 lines
1.3 KiB
Verilog
61 lines
1.3 KiB
Verilog
module top;
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reg a, q, qb;
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reg pass;
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always_comb q = a !== 1'bx;
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always_comb qb = a === 1'bx;
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initial begin
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pass = 1'b1;
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#0;
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// This second delay is needed for vlog95 since it uses #0 to create
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// the T0 trigger. vvp also needs it since it puts the event in the
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// inactive queue just like a #0 delay.
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#0;
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if (q !== 1'b0) begin
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$display("Expected q = 1'b0 with the default 1'bx input, got %b", q);
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pass = 1'b0;
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end
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if (qb !== 1'b1) begin
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$display("Expected qb = 1'b1 with the default 1'bx input, got %b", qb);
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pass = 1'b0;
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end
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#1;
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a = 1'b0;
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#0;
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if (q !== 1'b1) begin
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$display("Expected q = 1'b1 with an explicit 1'b0 input, got %b", q);
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pass = 1'b0;
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end
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#1;
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a = 1'b1;
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#0;
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if (q !== 1'b1) begin
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$display("Expected q = 1'b1 with an explicit 1'b1 input, got %b", q);
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pass = 1'b0;
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end
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#1;
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a = 1'bz;
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#0;
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if (q !== 1'b1) begin
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$display("Expected q = 1'b1 with an explicit 1'bz input, got %b", q);
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pass = 1'b0;
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end
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#1;
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a = 1'bx;
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#0;
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if (q !== 1'b0) begin
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$display("Expected q = 1'b0 with an explicit 1'bx input, got %b", q);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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