45 lines
991 B
Verilog
45 lines
991 B
Verilog
module top;
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logic passed;
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logic [7:0] value;
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integer ones;
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function automatic integer count_by_one(input integer start);
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if (start) count_by_one = (value[start] ? 1 : 0) + count_ones(start-1);
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else count_by_one = value[start] ? 1 : 0;
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endfunction
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function automatic integer count_ones(input integer start);
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if (start) count_ones = (value[start] ? 1 : 0) + count_by_one(start-1);
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else count_ones = value[start] ? 1 : 0;
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endfunction
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always_comb ones = count_ones(7);
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initial begin
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passed = 1'b1;
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value = 8'b0000_0000;
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#1;
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if (ones !== 0) begin
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$display("Expected 0, got %d", ones);
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passed = 1'b0;
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end
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value = 8'b0011_1100;
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#1;
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if (ones !== 4) begin
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$display("Expected 4, got %d", ones);
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passed = 1'b0;
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end
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value = 8'b1011_1101;
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#1;
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if (ones !== 6) begin
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$display("Expected 6, got %d", ones);
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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endmodule
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