57 lines
1.7 KiB
Verilog
57 lines
1.7 KiB
Verilog
//
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// Copyright (c) 1999 Steven Wilson (stevew@home.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW - Validate always for (expr1;boolean_expr;expr2) statement ;
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module main ;
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reg [3:0] value1,value2,value3;
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initial
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begin
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value1 = 0; // Time 0 assignemnt
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value2 = 0;
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#6 ;
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if(value1 != 4'h1)
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begin
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$display("FAILED - 3.1.7D always for (1)") ;
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value2 = 1;
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end
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#5 ;
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if(value1 != 4'h2)
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begin
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$display("FAILED - 3.1.7D always for (2) ");
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value2 = 1;
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end
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#5 ;
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if(value1 != 4'h3)
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begin
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$display("FAILED - 3.1.7D always for (3) ");
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value2 = 1;
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end
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if(value2 == 0)
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$display("PASSED");
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$finish;
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end
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always for(value1 = 0; value1 <= 5; value1 = value1 + 1) #5 ;
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endmodule
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