54 lines
929 B
Verilog
54 lines
929 B
Verilog
// (c) Alex.Perry@qm.com - 2002, Quantum Magnetics Inc, San Diego CA
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// This source file is licensed under the GNU public license version 2.0
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// All other rights reserved.
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// NOTE: This test catches addition of wide (>16 bits) constants
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// to wide vectors. -- Steve Williams
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module source ( C, h );
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output [ 0:0] C;
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output [11:0] h;
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reg [ 0:0] C;
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reg [11:0] h;
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reg [21:0] l;
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parameter kh = 3;
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parameter kl = 21'd364066;
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parameter wl = 21'h100000;
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initial #5
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begin
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C <= 0;
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l <= 0;
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h <= 0;
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end
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always #10 C = ~C;
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always @(posedge C)
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begin if ( l >= wl )
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begin l <= l + kl - wl;
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h <= h + kh + 1;
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end else
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begin l <= l + kl;
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h <= h + kh;
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end
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end
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endmodule
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module bench;
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wire [ 0:0] clock;
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wire [11:0] h;
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source dut ( .C(clock), .h(h) );
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initial #85
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begin
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if ( h == 13 ) begin
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$display ( "%7d", h );
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$display ("PASSED");
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end else begin
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$display ( "%7d = FAIL", h );
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end
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$finish;
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end
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endmodule
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