44 lines
893 B
Verilog
44 lines
893 B
Verilog
`timescale 1ns/10ps
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module top;
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reg pass;
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real result;
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initial begin
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pass = 1'b1;
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result = $abstime;
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if (result != 0.0) begin
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$display("FAILED at time 0, expected 0.0, got %g", result);
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pass = 1'b0;
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end
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#10;
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result = $abstime;
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if ($abs(result-10e-9) > result*1e-9) begin
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$display("FAILED at time 10ns, expected 1e-8, got %g", result);
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pass = 1'b0;
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end
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#999990;
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result = $abstime;
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if ($abs(result-0.001) > result*1e-9) begin
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$display("FAILED at time 1ms, expected 0.001, got %g", result);
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pass = 1'b0;
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end
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`ifdef __ICARUS_UNSIZED__
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#9999000000;
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`else
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#9999000000.0;
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`endif
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result = $abstime;
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if ($abs(result-10.0) > result*1e-9) begin
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$display("FAILED at time 10s, expected 10.0, got %g", result);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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