59 lines
1.5 KiB
Verilog
59 lines
1.5 KiB
Verilog
/*
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* Copyright (c) 2003 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*
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* $Id: timer_tb.v,v 1.1 2003/04/01 05:55:24 stevewilliams Exp $
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*/
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`timescale 1us / 1us
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module main;
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wire rdy;
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reg reset, clk;
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timer dut(.rdy(rdy), .clk(clk), .reset(reset));
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always begin
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#5 clk = 1;
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#5 clk = 0;
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end
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initial begin
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$dumpvars(0, main);
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#7 reset = 1;
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#1 if (rdy !== 0) begin
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$display("FAILED: reset did not clear rdy. rdy=%b", rdy);
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$finish;
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end
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#6 reset = 0;
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end
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always @(posedge clk)
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if (rdy === 1) begin
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$display("rdy=%b at time=%0d", rdy, $time);
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if ($time != 175) begin
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$display("FAILED: timer ran out incorrectly.");
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule // main
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