34 lines
1.1 KiB
Verilog
34 lines
1.1 KiB
Verilog
/*
|
|
* Copyright (c) 2003 Stephen Williams (steve@icarus.com)
|
|
*
|
|
* This source code is free software; you can redistribute it
|
|
* and/or modify it in source code form under the terms of the GNU
|
|
* General Public License as published by the Free Software
|
|
* Foundation; either version 2 of the License, or (at your option)
|
|
* any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
|
*
|
|
* $Id: timer.v,v 1.1 2003/04/01 05:55:24 stevewilliams Exp $
|
|
*/
|
|
|
|
module timer(output wire rdy, input wire clk, input wire reset);
|
|
|
|
reg [4:0] count;
|
|
assign rdy = count[4];
|
|
|
|
always @(posedge clk or posedge reset)
|
|
if (reset)
|
|
count <= 5'h0f;
|
|
else
|
|
count <= count - 1;
|
|
|
|
endmodule // timer
|