25 lines
560 B
Verilog
25 lines
560 B
Verilog
module main;
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reg [4:0] val;
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ornor4 dut (.O_OR(o_or), .O_NOR(o_nor),
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.I0(val[0]), .I1(val[1]), .I2(val[2]), .I3(val[3]));
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initial begin
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for (val = 0 ; val[4] == 0 ; val = val+1) begin
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#1 if (o_or !== |val[3:0]) begin
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$display("FAILED -- |%b --> %b", val[3:0], o_or);
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$finish;
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end
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if (o_nor !== ~|val[3:0]) begin
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$display("FAILED -- ~|%b --> %b", val[3:0], o_nor);
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$finish;
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end
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end // for (val = 0 ; val[4] == 0 ; val = val+1)
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$display("PASSED");
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end // initial begin
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endmodule // main
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