57 lines
1.5 KiB
Verilog
57 lines
1.5 KiB
Verilog
/*
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* Copyright (c) 2003 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*
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* $Id: onehot16_tb.v,v 1.1 2003/03/31 01:35:05 stevewilliams Exp $
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*/
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/*
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* Exhaustive check of all the subtract results.
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*/
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module main;
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wire [15:0] out;
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reg [3:0] A;
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onehot16 dut(.out(out), .A(A));
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reg error = 0;
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integer adx;
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initial begin
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A = 0;
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for (adx = 0 ; adx < 16 ; adx = adx + 1) begin
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A = adx;
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#1 $write("onehot(%b): %b", A, out);
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if (out !== (1 << adx)) begin
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$display(" ERROR");
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error = 1;
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end else begin
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$display(" OK");
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end
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end // for (adx = 0 ; adx < 256 ; adx = adx + 1)
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if (error == 0)
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$display("PASSED");
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else
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$display("FAILED");
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end // initial begin
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endmodule // main
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