55 lines
1.1 KiB
Verilog
55 lines
1.1 KiB
Verilog
/*
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* Exhaustive check of all the compare results.
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*/
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module main;
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wire out;
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reg [7:0] A, B;
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ge8 dut(.out(out), .A(A), .B(B));
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reg error = 0;
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integer adx, bdx;
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initial begin
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A = 0;
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B = 0;
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#1 $display("%b >= %b: %b", A, B, out);
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for (adx = 0 ; adx < 256 ; adx = adx + 1) begin
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A = adx;
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for (bdx = 0 ; bdx < 256 ; bdx = bdx + 1) begin
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B = bdx;
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#1 $write("%b >= %b: %b", A, B, out);
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if (out === 1) begin
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if (A < B) begin
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$display(" ERROR");
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error = 1;
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end else begin
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$display(" OK");
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end
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end else if (out === 0) begin
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if (A < B) begin
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$display(" OK");
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end else begin
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$display(" ERROR");
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error = 1;
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end
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end else begin
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$display(" ERROR");
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error = 1;
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end // else: !if(out === 0)
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end // for (bdx = 0 ; bdx < 256 ; bdx += 1)
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end // for (adx = 0 ; adx < 256 ; adx = adx + 1)
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if (error == 0)
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$display("PASSED");
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else
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$display("FAILED");
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end // initial begin
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endmodule // main
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