63 lines
1.1 KiB
Verilog
63 lines
1.1 KiB
Verilog
module main;
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wire out;
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reg [1:0] A, B;
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ge2 dut(.out(out), .A(A), .B(B));
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initial begin
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A = 0;
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B = 0;
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#1 $display("%b >= %b: %b", A, B, out);
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B = 1;
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#1 $display("%b >= %b: %b", A, B, out);
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B = 2;
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#1 $display("%b >= %b: %b", A, B, out);
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B = 3;
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#1 $display("%b >= %b: %b", A, B, out);
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A = 1;
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B = 0;
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#1 $display("%b >= %b: %b", A, B, out);
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B = 1;
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#1 $display("%b >= %b: %b", A, B, out);
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B = 2;
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#1 $display("%b >= %b: %b", A, B, out);
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B = 3;
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#1 $display("%b >= %b: %b", A, B, out);
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A = 2;
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B = 0;
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#1 $display("%b >= %b: %b", A, B, out);
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B = 1;
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#1 $display("%b >= %b: %b", A, B, out);
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B = 2;
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#1 $display("%b >= %b: %b", A, B, out);
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B = 3;
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#1 $display("%b >= %b: %b", A, B, out);
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A = 3;
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B = 0;
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#1 $display("%b >= %b: %b", A, B, out);
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B = 1;
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#1 $display("%b >= %b: %b", A, B, out);
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B = 2;
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#1 $display("%b >= %b: %b", A, B, out);
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B = 3;
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#1 $display("%b >= %b: %b", A, B, out);
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end // initial begin
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endmodule // main
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