53 lines
1.0 KiB
Verilog
53 lines
1.0 KiB
Verilog
module main;
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wire eq1, eq2, eq5;
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wire ne1, ne2, ne5;
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reg [7:0] x, y;
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eqne dut(.eq1(eq1), .eq2(eq2), .eq5(eq5),
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.ne1(ne1), .ne2(ne2), .ne5(ne5),
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.x(x), .y(y));
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initial begin
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for (x = 0 ; x < 'h20 ; x = x+1)
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for (y = 0 ; y < 'h20 ; y = y+1) begin
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#1 $display("x=%h, y=%h: ", x, y,
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"eq1=%b, eq2=%b, eq5=%b, ", eq1, eq2, eq5,
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"ne1=%b, ne2=%b, ne5=%b", ne1, ne2, ne5);
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if (eq1 !== (x[0] == y[0])) begin
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$display("FAILED");
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$finish;
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end
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if (eq2 !== (x[1:0] == y[1:0])) begin
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$display("FAILED");
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$finish;
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end
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if (eq5 !== (x[4:0] == y[4:0])) begin
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$display("FAILED");
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$finish;
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end
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if (ne1 !== (x[0] != y[0])) begin
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$display("FAILED");
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$finish;
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end
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if (ne2 !== (x[1:0] != y[1:0])) begin
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$display("FAILED");
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$finish;
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end
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if (ne5 !== (x[4:0] != y[4:0])) begin
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$display("FAILED");
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$finish;
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end
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end
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$display("PASSED");
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end
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endmodule // main
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