46 lines
784 B
Verilog
Executable File
46 lines
784 B
Verilog
Executable File
`timescale 100 ps / 10 ps
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module main;
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wire Q;
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reg D, G;
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LD u1 (.Q(Q), .D(D), .G(G));
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initial begin
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D = 0;
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G = 1;
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#1 if (Q !== 0) begin
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$display("FAILED -- D=%b, G=%b --> Q=%b", D, G, Q);
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$finish;
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end
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D = 1;
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#1 if (Q !== 1) begin
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$display("FAILED -- D=%b, G=%b --> Q=%b", D, G, Q);
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$finish;
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end
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G = 0;
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#1 if (Q !== 1) begin
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$display("FAILED -- D=%b, G=%b --> Q=%b", D, G, Q);
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$finish;
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end
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D = 0;
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#1 if (Q !== 1) begin
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$display("FAILED -- D=%b, G=%b --> Q=%b", D, G, Q);
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$finish;
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end
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G = 1;
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#1 if (Q !== 0) begin
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$display("FAILED -- D=%b, G=%b --> Q=%b", D, G, Q);
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule // main
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