32 lines
666 B
Verilog
32 lines
666 B
Verilog
module main;
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reg [2:0] i;
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wire out0, out1;
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wire ref0, ref1;
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bufifab dut(.Out0(out0), .Out1(out1), .I(i[0]), .E(i[1]));
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bufif0 (ref0, i[0], i[1]);
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bufif1 (ref1, i[0], i[1]);
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initial begin
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i = 0;
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for (i = 0 ; i[2] == 0 ; i = i+1) begin
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#1 $display("I=%b, E=%b, Out0=%b, Out1=%b", i[0], i[1], out0, out1);
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if (out0 !== ref0) begin
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$display("FAILED -- ref0=%b, out0=%b", ref0, out0);
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$finish;
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end
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if (out1 !== ref1) begin
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$display("FAILED -- ref1=%b, out1=%b", ref1, out1);
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$finish;
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end
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end // for (i = 0 ; i[2] == 0 ; i = i+1)
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$display("PASSED");
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end
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endmodule // main
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