49 lines
761 B
Verilog
49 lines
761 B
Verilog
module add32(sum, cOut, clock, a, b, cIn);
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input clock;
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input a, b, cIn;
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output sum, cOut;
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reg [31:0] a, b;
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reg cIn;
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wire [31:0] sum;
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wire cOut;
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always @(posedge clock)
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//{cOut, sum} = a + b + cIn;
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assign sum = a + b + cIn;
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endmodule
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//////////////////////////
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module main;
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reg CLOCK;
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reg [31:0] A, B;
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reg C_IN;
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reg [31:0] SUM;
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wire C_OUT;
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add32 myAdder(SUM, C_OUT, CLOCK, A, B, C_OUT);
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always #1 CLOCK = ~ CLOCK;
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initial
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begin
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$monitor($time,, " CLOCK=%d, A=%x, B=%x, C_IN=%d -- SUM=%x, C_OUT=%d",
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CLOCK, A, B, C_IN, SUM, C_OUT);
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end
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initial
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begin
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CLOCK = 0;
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A = 32'h00000001;
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B = 32'h00000002;
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C_IN = 1'b0;
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#20 $finish;
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end
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endmodule
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