54 lines
699 B
Verilog
54 lines
699 B
Verilog
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module cmpN
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#(parameter WID = 4)
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(input wire [WID-1:0] A,
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input wire [WID-1:0] B,
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output reg QE, QN, QGT, QGE
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/* */);
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always @(A, B)
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if (A > B)
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QGT = 1;
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else
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QGT = 0;
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always @(A, B)
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if (A >= B)
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QGE = 1;
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else
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QGE = 0;
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always @(A, B)
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if (A == B)
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QE = 1;
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else
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QE = 0;
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always @(A, B)
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if (A != B)
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QN = 1;
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else
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QN = 0;
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/*
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always @(A, B)
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if (A > B) begin
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QE = 0;
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QN = 1;
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QGT = 1;
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QGE = 1;
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end else if (A == B) begin
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QE = 1;
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QN = 0;
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QGT = 0;
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QGE = 1;
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end else begin
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QE = 0;
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QN = 1;
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QGT = 0;
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QGE = 0;
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end
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*/
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endmodule // add
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