33 lines
663 B
Verilog
33 lines
663 B
Verilog
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module main;
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parameter WID = 4;
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parameter SWID = 2;
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reg [WID-1:0] D;
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reg [SWID-1:0] S;
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wire Q;
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muxN dut(.\D[3] (D[3]), .\D[2] (D[2]), .\D[1] (D[1]), .\D[0] (D[0]),
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.\S[1] (S[1]), .\S[0] (S[0]),
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.Q(Q));
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integer idx, sdx;
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initial begin
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for (idx = 0 ; idx < 50 ; idx += 1) begin
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D = $random;
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for (sdx = 0 ; sdx < (1<<SWID) ; sdx = sdx+1) begin
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S = sdx[SWID-1:0];
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#1 ;
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if (Q !== D[S]) begin
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$display("FAILED = D=%b, S=%0d, Q=%b", D, S, Q);
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$finish;
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end
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end
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end // for (idx = 0 ; idx < 50 ; idx += 1)
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$display("PASSED");
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end // initial begin
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endmodule // main
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