35 lines
796 B
Verilog
35 lines
796 B
Verilog
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module main;
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reg [2:0] X;
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wire q_nand, q_nor, q_xnor, q_not;
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test_logic DUT(.A(X[0]), .B(X[1]), .q_nand(q_nand), .q_nor(q_nor),
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.q_xnor(q_xnor), .q_not(q_not));
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initial begin
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for (X = 0 ; X < 4 ; X = X+1) begin
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#1 /* Let gates settle. */;
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if (q_nand !== (X[0] ~& X[1])) begin
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$display("FAILED -- q_nand=%b, X=%b", q_nand, X[1:0]);
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$finish;
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end
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if (q_nor !== (X[0] ~| X[1])) begin
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$display("FAILED -- q_nor=%b, X=%b", q_nor, X[1:0]);
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$finish;
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end
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if (q_xnor !== (X[0] ~^ X[1])) begin
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$display("FAILED -- q_xnor=%b, X=%b", q_xnor, X[1:0]);
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$finish;
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end
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if (q_not !== (~X[0])) begin
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$display("FAILED -- q_not=%b, X=%b", q_not, X[0]);
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$finish;
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end
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end
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$display("PASSED");
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end
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endmodule // main
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