41 lines
978 B
Verilog
41 lines
978 B
Verilog
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/*
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* Generate a combinational adder of any width. The width parameter can
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* be any integer value >0. The A and B inputs have WID bits, and the Q
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* output has WID+1 bits to include the overflow.
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*/
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module addN
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#(parameter WID = 4)
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(input wire [WID-1:0] A,
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input wire [WID-1:0] B,
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output wire [WID:0] Q
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/* */);
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wire [WID-1:0] Cout;
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/* The least significant slice has no Cin */
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add1 U0 (.A(A[0]), .B(B[0]), .Cin(1'b0), .Q(Q[0]), .Cout(Cout[0]));
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/* Generate all the remaining slices */
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genvar i;
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for (i = 1 ; i < WID ; i = i+1) begin : U
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add1 Un (.A(A[i]), .B(B[i]), .Cin(Cout[i-1]), .Q(Q[i]), .Cout(Cout[i]));
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end
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assign Q[WID] = Cout[WID-1];
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endmodule // add
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/*
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* This is a single-bit combinational adder used by the addH module
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* above.
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*/
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module add1(input A, input B, input Cin, output reg Q, output reg Cout);
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always @* begin
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Q = A ^ B ^ Cin;
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Cout = A&B | A&Cin | B&Cin;
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end
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endmodule // hadd
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