346 lines
9.5 KiB
C++
346 lines
9.5 KiB
C++
/*
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* Copyright (c) 2001-2021 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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# include "resolv.h"
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# include "schedule.h"
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# include "compile.h"
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# include "statistics.h"
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# include <iostream>
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# include <algorithm>
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# include <cassert>
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using namespace std;
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/*
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* The core functor for a resolver node stores all the input values
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* received by that node. This provides the necessary information
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* for implementing the $countdrivers system call. For efficiency,
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* the resolver is implemented using a balanced quaternary tree, so
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* the core functor also stores the current value for each branch
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* of the tree, to eliminate the need to re-evaluate branches whose
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* inputs haven't changed. The tree values are flattened into a linear
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* array, with the input values stored at the start of the array, then
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* the next level of branch values, and so on, down to the final array
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* array element which stores the current output value.
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*/
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resolv_core::resolv_core(unsigned nports, vvp_net_t*net)
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: nports_(nports), net_(net)
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{
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count_functors_resolv += 1;
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}
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resolv_core::~resolv_core()
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{
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}
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void resolv_core::recv_vec4_pv_(unsigned port, const vvp_vector4_t&bit,
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unsigned base, unsigned vwid)
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{
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unsigned wid = bit.size();
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vvp_vector4_t res (vwid);
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for (unsigned idx = 0 ; idx < base ; idx += 1)
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res.set_bit(idx, BIT4_Z);
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for (unsigned idx = 0 ; idx < wid && idx+base < vwid; idx += 1)
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res.set_bit(idx+base, bit.value(idx));
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for (unsigned idx = base+wid ; idx < vwid ; idx += 1)
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res.set_bit(idx, BIT4_Z);
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recv_vec4_(port, res);
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}
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void resolv_core::recv_vec8_pv_(unsigned port, const vvp_vector8_t&bit,
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unsigned base, unsigned vwid)
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{
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unsigned wid = bit.size();
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vvp_vector8_t res (vwid);
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for (unsigned idx = 0 ; idx < base ; idx += 1)
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res.set_bit(idx, vvp_scalar_t());
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for (unsigned idx = 0 ; idx < wid && idx+base < vwid; idx += 1)
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res.set_bit(idx+base, bit.value(idx));
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for (unsigned idx = base+wid ; idx < vwid ; idx += 1)
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res.set_bit(idx, vvp_scalar_t());
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recv_vec8_(port, res);
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}
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resolv_extend::resolv_extend(resolv_core*core, unsigned port_base)
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: core_(core), port_base_(port_base)
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{
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}
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resolv_extend::~resolv_extend()
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{
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}
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resolv_tri::resolv_tri(unsigned nports, vvp_net_t*net, vvp_scalar_t hiz_value)
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: resolv_core(nports, net), hiz_value_(hiz_value)
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{
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// count the input (leaf) nodes
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unsigned nnodes = nports;
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// add in the intermediate branch nodes
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while (nports > 4) {
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nports = (nports + 3) / 4;
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nnodes += nports;
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}
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// add one more node for storing the output value
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// (not needed if there is only one input)
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if (nnodes > 1)
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nnodes += 1;
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val_ = new vvp_vector8_t [nnodes];
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}
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resolv_tri::~resolv_tri()
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{
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delete[] val_;
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}
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void resolv_tri::recv_vec4_(unsigned port, const vvp_vector4_t&bit)
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{
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recv_vec8_(port, vvp_vector8_t(bit, 6,6 /* STRONG */));
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}
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void resolv_tri::recv_vec8_(unsigned port, const vvp_vector8_t&bit)
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{
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assert(port < nports_);
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if (val_[port].eeq(bit))
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return;
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val_[port] = bit;
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// Starting at the leaf level, work down the tree, resolving
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// the changed values. base is the first node in the current
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// level and span is the number of nodes at that level. ip
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// is the first node in the group of four nodes at that level
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// that include the node that has changed, and op is the node
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// at the next level that stores the resolved value from that
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// group.
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unsigned base = 0;
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unsigned span = nports_;
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while (span > 1) {
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unsigned next_base = base + span;
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unsigned ip = base + (port & ~0x3);
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unsigned op = next_base + (port / 4);
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unsigned ll = min(ip + 4, next_base);
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vvp_vector8_t out = val_[ip];
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for (ip = ip + 1; ip < ll; ip += 1) {
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if (val_[ip].size() == 0)
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continue;
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if (out.size() == 0)
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out = val_[ip];
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else
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out = resolve(out, val_[ip]);
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}
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if (val_[op].eeq(out))
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return;
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val_[op] = out;
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base = next_base;
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span = (span + 3) / 4;
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port = port / 4;
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}
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if (! hiz_value_.is_hiz()) {
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for (unsigned idx = 0 ; idx < val_[base].size() ; idx += 1) {
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val_[base].set_bit(idx, resolve(val_[base].value(idx),
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hiz_value_));
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}
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}
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net_->send_vec8(val_[base]);
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}
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void resolv_tri::count_drivers(unsigned bit_idx, unsigned counts[3])
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{
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for (unsigned idx = 0 ; idx < nports_ ; idx += 1) {
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if (val_[idx].size() == 0)
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continue;
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update_driver_counts(val_[idx].value(bit_idx).value(), counts);
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}
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}
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resolv_wired_logic::resolv_wired_logic(unsigned nports, vvp_net_t*net)
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: resolv_core(nports, net)
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{
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// count the input (leaf) nodes
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unsigned nnodes = nports;
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// add in the intermediate branch nodes
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while (nports > 4) {
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nports = (nports + 3) / 4;
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nnodes += nports;
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}
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// add one more node for storing the output value
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// (not needed if there is only one input)
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if (nnodes > 1)
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nnodes += 1;
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val_ = new vvp_vector4_t [nnodes];
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}
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resolv_wired_logic::~resolv_wired_logic()
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{
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delete[] val_;
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}
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void resolv_wired_logic::recv_vec4_(unsigned port, const vvp_vector4_t&bit)
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{
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assert(port < nports_);
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if (val_[port].eeq(bit))
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return;
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val_[port] = bit;
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// Starting at the leaf level, work down the tree, resolving
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// the changed values. base is the first node in the current
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// level and span is the number of nodes at that level. ip
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// is the first node in the group of four nodes at that level
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// that include the node that has changed, and op is the node
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// at the next level that stores the resolved value from that
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// group.
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unsigned base = 0;
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unsigned span = nports_;
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while (span > 1) {
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unsigned next_base = base + span;
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unsigned ip = base + (port & ~0x3);
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unsigned op = next_base + (port / 4);
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unsigned ll = min(ip + 4, next_base);
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vvp_vector4_t out = val_[ip];
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for (ip = ip + 1; ip < ll; ip += 1) {
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if (val_[ip].size() == 0)
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continue;
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if (out.size() == 0)
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out = val_[ip];
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else
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out = wired_logic_math_(out, val_[ip]);
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}
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if (val_[op].eeq(out))
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return;
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val_[op] = out;
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base = next_base;
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span = (span + 3) / 4;
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port = port / 4;
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}
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net_->send_vec4(val_[base], 0);
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}
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void resolv_wired_logic::recv_vec8_(unsigned port, const vvp_vector8_t&bit)
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{
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recv_vec4_(port, reduce4(bit));
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}
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void resolv_wired_logic::count_drivers(unsigned bit_idx, unsigned counts[3])
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{
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for (unsigned idx = 0 ; idx < nports_ ; idx += 1) {
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if (val_[idx].size() == 0)
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continue;
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update_driver_counts(val_[idx].value(bit_idx), counts);
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}
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}
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resolv_triand::resolv_triand(unsigned nports, vvp_net_t*net)
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: resolv_wired_logic(nports, net)
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{
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}
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resolv_triand::~resolv_triand()
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{
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}
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vvp_vector4_t resolv_triand::wired_logic_math_(vvp_vector4_t&a, vvp_vector4_t&b)
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{
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assert(a.size() == b.size());
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vvp_vector4_t out (a.size());
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for (unsigned idx = 0 ; idx < out.size() ; idx += 1) {
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vvp_bit4_t abit = a.value(idx);
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vvp_bit4_t bbit = b.value(idx);
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if (abit == BIT4_Z) {
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out.set_bit(idx, bbit);
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} else if (bbit == BIT4_Z) {
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out.set_bit(idx, abit);
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} else if (abit == BIT4_0 || bbit == BIT4_0) {
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out.set_bit(idx, BIT4_0);
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} else if (abit == BIT4_X || bbit == BIT4_X) {
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out.set_bit(idx, BIT4_X);
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} else {
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out.set_bit(idx, BIT4_1);
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}
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}
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return out;
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}
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resolv_trior::resolv_trior(unsigned nports, vvp_net_t*net)
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: resolv_wired_logic(nports, net)
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{
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}
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resolv_trior::~resolv_trior()
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{
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}
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vvp_vector4_t resolv_trior::wired_logic_math_(vvp_vector4_t&a, vvp_vector4_t&b)
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{
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assert(a.size() == b.size());
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vvp_vector4_t out (a.size());
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for (unsigned idx = 0 ; idx < out.size() ; idx += 1) {
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vvp_bit4_t abit = a.value(idx);
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vvp_bit4_t bbit = b.value(idx);
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if (abit == BIT4_Z) {
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out.set_bit(idx, bbit);
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} else if (bbit == BIT4_Z) {
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out.set_bit(idx, abit);
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} else if (abit == BIT4_1 || bbit == BIT4_1) {
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out.set_bit(idx, BIT4_1);
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} else if (abit == BIT4_X || bbit == BIT4_X) {
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out.set_bit(idx, BIT4_X);
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} else {
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out.set_bit(idx, BIT4_0);
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}
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}
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return out;
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}
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