737 lines
16 KiB
C++
737 lines
16 KiB
C++
/*
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* Copyright (c) 2001-2020 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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# include "logic.h"
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# include "compile.h"
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# include "bufif.h"
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# include "npmos.h"
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# include "schedule.h"
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# include "delay.h"
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# include "statistics.h"
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# include <iostream>
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# include <cstring>
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# include <cassert>
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# include <cstdlib>
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vvp_fun_boolean_::vvp_fun_boolean_(unsigned wid)
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{
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net_ = 0;
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for (unsigned idx = 0 ; idx < 4 ; idx += 1)
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input_[idx] = vvp_vector4_t(wid, BIT4_Z);
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}
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vvp_fun_boolean_::~vvp_fun_boolean_()
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{
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}
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void vvp_fun_boolean_::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit,
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vvp_context_t)
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{
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unsigned port = ptr.port();
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if (input_[port] .eeq( bit ))
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return;
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input_[port] = bit;
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if (net_ == 0) {
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net_ = ptr.ptr();
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schedule_functor(this);
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}
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}
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void vvp_fun_boolean_::recv_vec4_pv(vvp_net_ptr_t ptr, const vvp_vector4_t&bit,
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unsigned base, unsigned vwid, vvp_context_t)
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{
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unsigned port = ptr.port();
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assert(base + bit.size() <= vwid);
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// Set the part for the input. If nothing changes, then break.
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bool flag = input_[port] .set_vec(base, bit);
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if (flag == false)
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return;
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if (net_ == 0) {
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net_ = ptr.ptr();
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schedule_functor(this);
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}
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}
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vvp_fun_and::vvp_fun_and(unsigned wid, bool invert)
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: vvp_fun_boolean_(wid), invert_(invert)
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{
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count_functors_logic += 1;
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}
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vvp_fun_and::~vvp_fun_and()
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{
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}
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void vvp_fun_and::run_run()
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{
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vvp_net_t*ptr = net_;
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net_ = 0;
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vvp_vector4_t result (input_[0]);
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for (unsigned idx = 0 ; idx < result.size() ; idx += 1) {
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vvp_bit4_t bitbit = result.value(idx);
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for (unsigned pdx = 1 ; pdx < 4 ; pdx += 1) {
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if (input_[pdx].size() < idx) {
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bitbit = BIT4_X;
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break;
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}
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bitbit = bitbit & input_[pdx].value(idx);
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}
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if (invert_)
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bitbit = ~bitbit;
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result.set_bit(idx, bitbit);
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}
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ptr->send_vec4(result, 0);
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}
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vvp_fun_equiv::vvp_fun_equiv()
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: vvp_fun_boolean_(1)
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{
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count_functors_logic += 1;
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}
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vvp_fun_equiv::~vvp_fun_equiv()
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{
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}
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void vvp_fun_equiv::run_run()
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{
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vvp_net_t*ptr = net_;
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net_ = 0;
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assert(input_[0].size() == 1);
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assert(input_[1].size() == 1);
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vvp_bit4_t bit = ~(input_[0].value(0) ^ input_[1].value(0));
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vvp_vector4_t result (1, bit);
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ptr->send_vec4(result, 0);
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}
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vvp_fun_impl::vvp_fun_impl()
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: vvp_fun_boolean_(1)
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{
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count_functors_logic += 1;
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}
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vvp_fun_impl::~vvp_fun_impl()
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{
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}
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void vvp_fun_impl::run_run()
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{
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vvp_net_t*ptr = net_;
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net_ = 0;
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assert(input_[0].size() == 1);
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assert(input_[1].size() == 1);
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vvp_bit4_t bit = ~input_[0].value(0) | input_[1].value(0);
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vvp_vector4_t result (1, bit);
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ptr->send_vec4(result, 0);
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}
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vvp_fun_buf::vvp_fun_buf(unsigned wid)
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: input_(wid, BIT4_Z)
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{
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net_ = 0;
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count_functors_logic += 1;
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}
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vvp_fun_buf::~vvp_fun_buf()
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{
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}
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/*
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* The buf functor is very simple--change the z bits to x bits in the
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* vector it passes, and propagate the result.
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*/
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void vvp_fun_buf::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit,
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vvp_context_t)
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{
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if (ptr.port() != 0)
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return;
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if (input_ .eeq( bit ))
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return;
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input_ = bit;
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if (net_ == 0) {
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net_ = ptr.ptr();
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schedule_functor(this);
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}
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}
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void vvp_fun_buf::recv_vec4_pv(vvp_net_ptr_t ptr, const vvp_vector4_t&bit,
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unsigned base, unsigned vwid, vvp_context_t)
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{
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if (ptr.port() != 0)
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return;
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assert(base + bit.size() <= vwid);
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// Set the input part. If nothing changes, then break.
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bool flag = input_.set_vec(base, bit);
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if (flag == false)
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return;
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if (net_ == 0) {
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net_ = ptr.ptr();
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schedule_functor(this);
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}
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}
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void vvp_fun_buf::run_run()
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{
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vvp_net_t*ptr = net_;
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net_ = 0;
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vvp_vector4_t tmp (input_);
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tmp.change_z2x();
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ptr->send_vec4(tmp, 0);
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}
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vvp_fun_bufz::vvp_fun_bufz()
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{
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count_functors_logic += 1;
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}
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vvp_fun_bufz::~vvp_fun_bufz()
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{
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}
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/*
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* The bufz is similar to the buf device, except that it does not
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* bother translating z bits to x.
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*/
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void vvp_fun_bufz::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit,
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vvp_context_t)
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{
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if (ptr.port() != 0)
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return;
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ptr.ptr()->send_vec4(bit, 0);
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}
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void vvp_fun_bufz::recv_vec4_pv(vvp_net_ptr_t ptr, const vvp_vector4_t&bit,
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unsigned base, unsigned vwid, vvp_context_t)
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{
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if (ptr.port() != 0)
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return;
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ptr.ptr()->send_vec4_pv(bit, base, vwid, 0);
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}
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void vvp_fun_bufz::recv_real(vvp_net_ptr_t ptr, double bit,
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vvp_context_t)
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{
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if (ptr.port() != 0)
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return;
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ptr.ptr()->send_real(bit, 0);
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}
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void vvp_fun_buft::recv_vec8(vvp_net_ptr_t ptr, const vvp_vector8_t&bit)
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{
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if (ptr.port() != 0)
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return;
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ptr.ptr()->send_vec8(bit);
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}
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vvp_fun_muxr::vvp_fun_muxr()
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: a_(0.0), b_(0.0)
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{
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net_ = 0;
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count_functors_logic += 1;
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select_ = SEL_BOTH;
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}
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vvp_fun_muxr::~vvp_fun_muxr()
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{
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}
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void vvp_fun_muxr::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit,
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vvp_context_t)
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{
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/* The real valued mux can only take in the select as a
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vector4_t. The muxed data is real. */
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if (ptr.port() != 2)
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return;
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assert(bit.size() == 1);
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switch (bit.value(0)) {
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case BIT4_0:
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if (select_ == SEL_PORT0) return;
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select_ = SEL_PORT0;
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break;
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case BIT4_1:
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if (select_ == SEL_PORT1) return;
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select_ = SEL_PORT1;
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break;
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default:
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if (select_ == SEL_BOTH) return;
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select_ = SEL_BOTH;
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}
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if (net_ == 0) {
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net_ = ptr.ptr();
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schedule_functor(this);
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}
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}
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void vvp_fun_muxr::recv_real(vvp_net_ptr_t ptr, double bit,
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vvp_context_t)
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{
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switch (ptr.port()) {
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case 0:
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if (a_ == bit) return;
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a_ = bit;
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if (select_ == SEL_PORT1) return; // The other port is selected.
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break;
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case 1:
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if (b_ == bit) return;
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b_ = bit;
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if (select_ == SEL_PORT0) return; // The other port is selected.
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break;
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default:
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fprintf(stderr, "Unsupported port type %u.\n", ptr.port());
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assert(0);
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}
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if (net_ == 0) {
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net_ = ptr.ptr();
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schedule_functor(this);
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}
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}
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void vvp_fun_muxr::run_run()
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{
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vvp_net_t*ptr = net_;
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net_ = 0;
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switch (select_) {
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case SEL_PORT0:
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ptr->send_real(a_, 0);
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break;
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case SEL_PORT1:
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ptr->send_real(b_, 0);
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break;
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default:
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if (a_ == b_) {
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ptr->send_real(a_, 0);
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} else {
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ptr->send_real(0.0, 0); // Should this be NaN?
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}
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break;
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}
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}
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vvp_fun_muxz::vvp_fun_muxz(unsigned wid)
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: a_(wid, BIT4_Z), b_(wid, BIT4_Z)
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{
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net_ = 0;
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count_functors_logic += 1;
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select_ = SEL_BOTH;
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has_run_ = false;
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}
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vvp_fun_muxz::~vvp_fun_muxz()
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{
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}
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void vvp_fun_muxz::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit,
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vvp_context_t)
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{
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switch (ptr.port()) {
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case 0:
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if (a_ .eeq(bit) && has_run_) return;
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a_ = bit;
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if (select_ == SEL_PORT1) return; // The other port is selected.
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break;
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case 1:
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if (b_ .eeq(bit) && has_run_) return;
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b_ = bit;
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if (select_ == SEL_PORT0) return; // The other port is selected.
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break;
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case 2:
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assert(bit.size() == 1);
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switch (bit.value(0)) {
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case BIT4_0:
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if (select_ == SEL_PORT0) return;
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select_ = SEL_PORT0;
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break;
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case BIT4_1:
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if (select_ == SEL_PORT1) return;
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select_ = SEL_PORT1;
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break;
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default:
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if (select_ == SEL_BOTH && has_run_) return;
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select_ = SEL_BOTH;
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}
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break;
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default:
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return;
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}
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if (net_ == 0) {
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net_ = ptr.ptr();
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schedule_functor(this);
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}
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}
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void vvp_fun_muxz::recv_vec4_pv(vvp_net_ptr_t ptr, const vvp_vector4_t&bit,
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unsigned base, unsigned vwid, vvp_context_t)
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{
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assert(base + bit.size() <= vwid);
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bool flag;
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switch (ptr.port()) {
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case 0:
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flag = a_.set_vec(base, bit);
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if (flag == false && has_run_) return;
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if (select_ == SEL_PORT1) return; // The other port is selected.
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break;
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case 1:
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flag = b_.set_vec(base, bit);
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if (flag == false && has_run_) return;
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if (select_ == SEL_PORT0) return; // The other port is selected.
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break;
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case 2:
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assert((base == 0) && (bit.size() == 1));
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recv_vec4(ptr, bit, 0);
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default:
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return;
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}
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if (net_ == 0) {
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net_ = ptr.ptr();
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schedule_functor(this);
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}
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}
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void vvp_fun_muxz::run_run()
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{
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has_run_ = true;
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vvp_net_t*ptr = net_;
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net_ = 0;
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switch (select_) {
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case SEL_PORT0:
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ptr->send_vec4(a_, 0);
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break;
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case SEL_PORT1:
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ptr->send_vec4(b_, 0);
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break;
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default:
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{
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unsigned min_size = a_.size();
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unsigned max_size = min_size;
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if (b_.size() < min_size)
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min_size = b_.size();
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if (b_.size() > max_size)
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max_size = b_.size();
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vvp_vector4_t res (max_size);
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for (unsigned idx = 0 ; idx < min_size ; idx += 1) {
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if (a_.value(idx) == b_.value(idx))
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res.set_bit(idx, a_.value(idx));
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else
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res.set_bit(idx, BIT4_X);
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}
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for (unsigned idx = min_size ; idx < max_size ; idx += 1)
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res.set_bit(idx, BIT4_X);
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ptr->send_vec4(res, 0);
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}
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break;
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}
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}
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vvp_fun_not::vvp_fun_not(unsigned wid)
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: input_(wid, BIT4_Z)
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{
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net_ = 0;
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count_functors_logic += 1;
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}
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vvp_fun_not::~vvp_fun_not()
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{
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}
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/*
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* The not functor is very simple--change the z bits to x bits in the
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* vector it passes, and propagate the inverted result.
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*/
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void vvp_fun_not::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit,
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vvp_context_t)
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{
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if (ptr.port() != 0)
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return;
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if (input_ .eeq( bit ))
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return;
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input_ = bit;
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if (net_ == 0) {
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net_ = ptr.ptr();
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schedule_functor(this);
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}
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}
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void vvp_fun_not::recv_vec4_pv(vvp_net_ptr_t ptr, const vvp_vector4_t&bit,
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unsigned base, unsigned vwid, vvp_context_t)
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{
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if (ptr.port() != 0)
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return;
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assert(base + bit.size() <= vwid);
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// Set the part value. If nothing changes, then break.
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bool flag = input_.set_vec(base, bit);
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if (flag == false)
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return;
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if (net_ == 0) {
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net_ = ptr.ptr();
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schedule_functor(this);
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}
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}
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void vvp_fun_not::run_run()
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{
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vvp_net_t*ptr = net_;
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net_ = 0;
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vvp_vector4_t result (input_, true /* invert */);
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ptr->send_vec4(result, 0);
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}
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vvp_fun_or::vvp_fun_or(unsigned wid, bool invert)
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: vvp_fun_boolean_(wid), invert_(invert)
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{
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count_functors_logic += 1;
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}
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vvp_fun_or::~vvp_fun_or()
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{
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}
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void vvp_fun_or::run_run()
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{
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vvp_net_t*ptr = net_;
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net_ = 0;
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vvp_vector4_t result (input_[0]);
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for (unsigned idx = 0 ; idx < result.size() ; idx += 1) {
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vvp_bit4_t bitbit = result.value(idx);
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for (unsigned pdx = 1 ; pdx < 4 ; pdx += 1) {
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if (input_[pdx].size() < idx) {
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bitbit = BIT4_X;
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break;
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}
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bitbit = bitbit | input_[pdx].value(idx);
|
|
}
|
|
|
|
if (invert_)
|
|
bitbit = ~bitbit;
|
|
result.set_bit(idx, bitbit);
|
|
}
|
|
|
|
ptr->send_vec4(result, 0);
|
|
}
|
|
|
|
vvp_fun_xor::vvp_fun_xor(unsigned wid, bool invert)
|
|
: vvp_fun_boolean_(wid), invert_(invert)
|
|
{
|
|
count_functors_logic += 1;
|
|
}
|
|
|
|
vvp_fun_xor::~vvp_fun_xor()
|
|
{
|
|
}
|
|
|
|
void vvp_fun_xor::run_run()
|
|
{
|
|
vvp_net_t*ptr = net_;
|
|
net_ = 0;
|
|
|
|
vvp_vector4_t result (input_[0]);
|
|
|
|
for (unsigned idx = 0 ; idx < result.size() ; idx += 1) {
|
|
vvp_bit4_t bitbit = result.value(idx);
|
|
for (unsigned pdx = 1 ; pdx < 4 ; pdx += 1) {
|
|
if (input_[pdx].size() < idx) {
|
|
bitbit = BIT4_X;
|
|
break;
|
|
}
|
|
|
|
bitbit = bitbit ^ input_[pdx].value(idx);
|
|
}
|
|
|
|
if (invert_)
|
|
bitbit = ~bitbit;
|
|
result.set_bit(idx, bitbit);
|
|
}
|
|
|
|
ptr->send_vec4(result, 0);
|
|
}
|
|
|
|
/*
|
|
* The parser calls this function to create a logic functor. I allocate a
|
|
* functor, and map the name to the vvp_ipoint_t address for the
|
|
* functor. Also resolve the inputs to the functor.
|
|
*/
|
|
|
|
void compile_functor(char*label, char*type, unsigned width,
|
|
unsigned ostr0, unsigned ostr1,
|
|
unsigned argc, struct symb_s*argv)
|
|
{
|
|
vvp_net_fun_t* obj = 0;
|
|
bool strength_aware = false;
|
|
|
|
if (strcmp(type, "OR") == 0) {
|
|
obj = new vvp_fun_or(width, false);
|
|
|
|
} else if (strcmp(type, "AND") == 0) {
|
|
obj = new vvp_fun_and(width, false);
|
|
|
|
} else if (strcmp(type, "BUF") == 0) {
|
|
obj = new vvp_fun_buf(width);
|
|
|
|
} else if (strcmp(type, "BUFIF0") == 0) {
|
|
obj = new vvp_fun_bufif(true,false, ostr0, ostr1);
|
|
strength_aware = true;
|
|
|
|
} else if (strcmp(type, "BUFIF1") == 0) {
|
|
obj = new vvp_fun_bufif(false,false, ostr0, ostr1);
|
|
strength_aware = true;
|
|
|
|
} else if (strcmp(type, "EQUIV") == 0) {
|
|
obj = new vvp_fun_equiv();
|
|
|
|
} else if (strcmp(type, "IMPL") == 0) {
|
|
obj = new vvp_fun_impl();
|
|
|
|
} else if (strcmp(type, "NAND") == 0) {
|
|
obj = new vvp_fun_and(width, true);
|
|
|
|
} else if (strcmp(type, "NOR") == 0) {
|
|
obj = new vvp_fun_or(width, true);
|
|
|
|
} else if (strcmp(type, "NOTIF0") == 0) {
|
|
obj = new vvp_fun_bufif(true,true, ostr0, ostr1);
|
|
strength_aware = true;
|
|
|
|
} else if (strcmp(type, "NOTIF1") == 0) {
|
|
obj = new vvp_fun_bufif(false,true, ostr0, ostr1);
|
|
strength_aware = true;
|
|
|
|
} else if (strcmp(type, "BUFT") == 0) {
|
|
obj = new vvp_fun_buft();
|
|
|
|
} else if (strcmp(type, "BUFZ") == 0) {
|
|
obj = new vvp_fun_bufz();
|
|
|
|
} else if (strcmp(type, "MUXR") == 0) {
|
|
obj = new vvp_fun_muxr;
|
|
|
|
} else if (strcmp(type, "MUXZ") == 0) {
|
|
obj = new vvp_fun_muxz(width);
|
|
|
|
} else if (strcmp(type, "CMOS") == 0) {
|
|
obj = new vvp_fun_cmos();
|
|
|
|
} else if (strcmp(type, "NMOS") == 0) {
|
|
obj = new vvp_fun_pmos(true);
|
|
|
|
} else if (strcmp(type, "PMOS") == 0) {
|
|
obj = new vvp_fun_pmos(false);
|
|
|
|
} else if (strcmp(type, "RCMOS") == 0) {
|
|
obj = new vvp_fun_rcmos();
|
|
|
|
} else if (strcmp(type, "RNMOS") == 0) {
|
|
obj = new vvp_fun_rpmos(true);
|
|
|
|
} else if (strcmp(type, "RPMOS") == 0) {
|
|
obj = new vvp_fun_rpmos(false);
|
|
|
|
} else if (strcmp(type, "NOT") == 0) {
|
|
obj = new vvp_fun_not(width);
|
|
|
|
} else if (strcmp(type, "XNOR") == 0) {
|
|
obj = new vvp_fun_xor(width, true);
|
|
|
|
} else if (strcmp(type, "XOR") == 0) {
|
|
obj = new vvp_fun_xor(width, false);
|
|
|
|
} else {
|
|
yyerror("invalid functor type.");
|
|
free(type);
|
|
free(argv);
|
|
free(label);
|
|
return;
|
|
}
|
|
|
|
free(type);
|
|
|
|
assert(argc <= 4);
|
|
vvp_net_t*net = new vvp_net_t;
|
|
net->fun = obj;
|
|
|
|
inputs_connect(net, argc, argv);
|
|
free(argv);
|
|
|
|
/* If both the strengths are the default strong drive, then
|
|
there is no need for a specialized driver. Attach the label
|
|
to this node and we are finished. */
|
|
if (strength_aware || (ostr0 == 6 && ostr1 == 6)) {
|
|
define_functor_symbol(label, net);
|
|
free(label);
|
|
return;
|
|
}
|
|
|
|
vvp_net_t*net_drv = new vvp_net_t;
|
|
vvp_net_fun_t*obj_drv = new vvp_fun_drive(ostr0, ostr1);
|
|
net_drv->fun = obj_drv;
|
|
|
|
/* Point the gate to the drive node. */
|
|
net->link(vvp_net_ptr_t(net_drv, 0));
|
|
|
|
define_functor_symbol(label, net_drv);
|
|
free(label);
|
|
}
|