201 lines
6.0 KiB
C++
201 lines
6.0 KiB
C++
/*
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* VHDL implementation of $display.
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*
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* Copyright (C) 2008-2009 Nick Gasson (nick@nickg.me.uk)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include "vhdl_target.h"
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#include <iostream>
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#include <cstring>
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#include <cassert>
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#include <cctype>
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#include <sstream>
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static const char *DISPLAY_LINE = "Verilog_Display_Line";
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/*
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* Write a VHDL expression into the current display line.
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*/
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static void display_write(stmt_container *container, vhdl_expr *expr)
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{
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vhdl_pcall_stmt *write = new vhdl_pcall_stmt("Write");
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vhdl_var_ref *ref =
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new vhdl_var_ref(DISPLAY_LINE, vhdl_type::line());
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write->add_expr(ref);
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vhdl_type_name_t type = expr->get_type()->get_name();
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if (type == VHDL_TYPE_SIGNED || type == VHDL_TYPE_UNSIGNED) {
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vhdl_type integer(VHDL_TYPE_INTEGER);
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write->add_expr(expr->cast(&integer));
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}
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else if (type != VHDL_TYPE_STRING) {
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// Need to add a call to Type'Image for types not
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// supported by std.textio
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std::string name(expr->get_type()->get_string());
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name += "'Image";
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vhdl_fcall *cast
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= new vhdl_fcall(name.c_str(), vhdl_type::string());
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cast->add_expr(expr);
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write->add_expr(cast);
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}
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else
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write->add_expr(expr);
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container->add_stmt(write);
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}
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/*
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* Write the value of DISPLAY_LINE to the output.
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*/
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static void display_line(stmt_container *container)
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{
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vhdl_pcall_stmt *write_line = new vhdl_pcall_stmt("WriteLine");
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vhdl_var_ref *output_ref =
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new vhdl_var_ref("std.textio.Output", new vhdl_type(VHDL_TYPE_FILE));
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write_line->add_expr(output_ref);
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vhdl_var_ref *ref =
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new vhdl_var_ref(DISPLAY_LINE, vhdl_type::line());
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write_line->add_expr(ref);
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container->add_stmt(write_line);
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}
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/*
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* Parse an octal escape sequence.
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*/
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static char parse_octal(const char *p)
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{
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assert(*p && *(p+1) && *(p+2));
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assert(isdigit(*p) && isdigit(*(p+1)) && isdigit(*(p+1)));
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return (*p - '0') * 64
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+ (*(p+1) - '0') * 8
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+ (*(p+2) - '0') * 1;
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}
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static void flush_string(std::ostringstream &ss, stmt_container *container)
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{
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display_write(container, new vhdl_const_string(ss.str().c_str()));
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// Clear the stream
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ss.str("");
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}
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// This should display the hierarchical module name, but we don't support
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// this in VHDL. So just emit a warning.
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static void display_m(stmt_container* container)
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{
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cerr << "Warning: no VHDL translation for %m format code" << endl;
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}
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/*
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* Generate VHDL for the $display system task.
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* This is implemented using the functions in std.textio. Each
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* parameter is written to a line variable in the process and
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* then the line is written to the special variable `Output'
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* (which represents the console). Subsequent $displays will
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* use the same line variable.
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*
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* It's possible, although quite unlikely, that there will be
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* name collision with an existing variable called
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* `Verilog_Display_Line' -- do something about this?
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*/
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int draw_stask_display(vhdl_procedural *proc, stmt_container *container,
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ivl_statement_t stmt, bool newline)
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{
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if (!proc->get_scope()->have_declared(DISPLAY_LINE)) {
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vhdl_var_decl *line_var =
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new vhdl_var_decl(DISPLAY_LINE, vhdl_type::line());
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line_var->set_comment("For generating $display output");
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proc->get_scope()->add_decl(line_var);
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}
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// Write the data into the line
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int count = ivl_stmt_parm_count(stmt), i = 0;
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while (i < count) {
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// $display may have an empty parameter, in which case
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// the expression will be null
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// The behaviour here seems to be to output a space
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ivl_expr_t net = ivl_stmt_parm(stmt, i++);
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if (net == NULL) {
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display_write(container, new vhdl_const_string(" "));
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continue;
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}
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if (ivl_expr_type(net) == IVL_EX_STRING) {
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ostringstream ss;
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for (const char *p = ivl_expr_string(net); *p; p++) {
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if (*p == '\\') {
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// Octal escape
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char ch = parse_octal(p+1);
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if (ch == '\n') {
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flush_string(ss, container);
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display_line(container);
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}
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else
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ss << ch;
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p += 3;
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}
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else if (*p == '%' && *(++p) != '%') {
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flush_string(ss, container);
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// Skip over width for now
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while (isdigit(*p)) ++p;
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switch (*p) {
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case 'm':
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display_m(container);
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break;
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default:
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{
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assert(i < count);
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ivl_expr_t netp = ivl_stmt_parm(stmt, i++);
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assert(netp);
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vhdl_expr *base = translate_expr(netp);
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if (NULL == base)
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return 1;
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display_write(container, base);
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}
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}
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}
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else
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ss << *p;
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}
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// Call Write on any non-empty string data left in the buffer
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if (!ss.str().empty())
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display_write(container, new vhdl_const_string(ss.str().c_str()));
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}
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else {
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vhdl_expr *base = translate_expr(net);
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if (NULL == base)
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return 1;
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display_write(container, base);
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}
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}
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if (newline)
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display_line(container);
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return 0;
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}
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