231 lines
7.1 KiB
C++
231 lines
7.1 KiB
C++
/*
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* Copyright (c) 1999 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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# include "config.h"
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/*
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* This functor scans the design looking for dangling objects and
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* excess local signals. These deletions are not necessarily required
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* for proper functioning of anything, but they can clean up the
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* appearance of design files that are generated.
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*/
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# include "functor.h"
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# include "netlist.h"
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# include "compiler.h"
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class nodangle_f : public functor_t {
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public:
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void event(Design*des, NetEvent*ev);
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void signal(Design*des, NetNet*sig);
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unsigned iteration;
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unsigned stotal, etotal;
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bool scontinue, econtinue;
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bool scomplete, ecomplete;
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};
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void nodangle_f::event(Design*des, NetEvent*ev)
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{
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if (ecomplete) return;
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/* If there are no references to this event, then go right
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ahead and delete it. There is no use looking further at
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it. */
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if ((ev->nwait() + ev->ntrig() + ev->nexpr()) == 0) {
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delete ev;
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etotal += 1;
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return;
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}
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if (iteration == 0) {
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/* Try to remove duplicate probes from the event. This
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is done as a separate initial pass to ensure similar
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events are detected as soon as possible in subsequent
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iterations. */
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for (unsigned idx = 0 ; idx < ev->nprobe() ; idx += 1) {
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unsigned jdx = idx + 1;
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while (jdx < ev->nprobe()) {
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NetEvProbe*ip = ev->probe(idx);
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NetEvProbe*jp = ev->probe(jdx);
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if (ip->edge() != jp->edge()) {
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jdx += 1;
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continue;
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}
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bool fully_connected = true;
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for (unsigned jpin = 0; jpin < jp->pin_count(); jpin += 1) {
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unsigned ipin = 0;
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bool connected_flag = false;
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for (ipin = 0 ; ipin < ip->pin_count(); ipin += 1)
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if (connected(ip->pin(ipin), jp->pin(jpin))) {
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connected_flag = true;
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break;
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}
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if (!connected_flag) {
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fully_connected = false;
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break;
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}
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}
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if (fully_connected) {
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delete jp;
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} else {
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jdx += 1;
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}
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}
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}
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econtinue = true;
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} else {
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/* Postpone examining events in an automatic scope until the
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third (optional) pass. This will mean similar events are
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biased towards being stored in static scopes. */
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if (ev->scope()->is_auto()) {
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if (iteration == 1) {
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econtinue = true;
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return;
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}
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} else {
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if (iteration == 2) {
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return;
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}
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}
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/* Try to find all the events that are similar to me, and
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replace their references with references to me. */
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list<NetEvent*> match;
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ev->find_similar_event(match);
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for (list<NetEvent*>::iterator idx = match.begin()
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; idx != match.end() ; idx ++) {
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NetEvent*tmp = *idx;
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assert(tmp != ev);
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tmp ->replace_event(ev);
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}
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}
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}
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void nodangle_f::signal(Design*des, NetNet*sig)
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{
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if (scomplete) return;
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/* Cannot delete signals referenced in an expression
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or an l-value. */
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if (sig->get_refs() > 0)
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return;
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/* Cannot delete the ports of tasks or functions. There are
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too many places where they are referenced. */
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if ((sig->port_type() != NetNet::NOT_A_PORT)
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&& (sig->scope()->type() == NetScope::TASK))
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return;
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if ((sig->port_type() != NetNet::NOT_A_PORT)
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&& (sig->scope()->type() == NetScope::FUNC))
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return;
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/* Can't delete ports of cells. */
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if ((sig->port_type() != NetNet::NOT_A_PORT)
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&& (sig->scope()->attribute(perm_string::literal("ivl_synthesis_cell")) != verinum()))
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return;
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/* Check to see if the signal is completely unconnected. If
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all the bits are unlinked, then delete it. */
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bool linked_flag = false;
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for (unsigned idx = 0 ; idx < sig->pin_count() ; idx += 1)
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if (sig->pin(idx).is_linked()) {
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linked_flag = true;
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break;
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}
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if (! linked_flag) {
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delete sig;
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stotal += 1;
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return;
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}
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/* The remaining things can only be done to synthesized
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signals, not ones that appear in the original Verilog. */
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if (! sig->local_flag())
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return;
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/* Check to see if there is some significant signal connected
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to every pin of this signal. */
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unsigned significant_flags = 0;
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for (unsigned idx = 0 ; idx < sig->pin_count() ; idx += 1) {
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Nexus*nex = sig->pin(idx).nexus();
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for (Link*cur = nex->first_nlink()
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; cur ; cur = cur->next_nlink()) {
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if (cur == &sig->pin(idx))
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continue;
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NetNet*cursig = dynamic_cast<NetNet*>(cur->get_obj());
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if (cursig == 0)
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continue;
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if (cursig->local_flag())
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continue;
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significant_flags += 1;
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break;
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}
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if (significant_flags <= idx)
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break;
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}
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/* If every pin is connected to another significant signal,
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then I can delete this one. */
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if (significant_flags == sig->pin_count()) {
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scontinue = true;
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delete sig;
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stotal += 1;
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}
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}
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void nodangle(Design*des)
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{
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nodangle_f fun;
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fun.iteration = 0;
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fun.stotal = 0;
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fun.etotal = 0;
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fun.scomplete = false;
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fun.ecomplete = false;
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do {
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fun.scontinue = false;
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fun.econtinue = false;
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des->functor(&fun);
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fun.iteration += 1;
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fun.scomplete = !fun.scontinue;
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fun.ecomplete = !fun.econtinue;
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if (verbose_flag) {
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cout << " ... " << fun.iteration << " iterations"
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<< " deleted " << fun.stotal << " dangling signals"
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<< " and " << fun.etotal << " events." << endl;
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}
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} while (fun.scontinue || fun.econtinue);
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}
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