Files
iverilog/vvp/bufif.h
T
Lars-Peter Clausen 2032e14f5a vvp: Remove wid parameter from recv_vec{4,8}_pv()
The `recv_vec{4,8}_pv()` functions are used to implement a partial write to
a vector. As parameters they take both the value and the width of the
value.

All callers of of these functions pass `val.size()` or a variation thereof
as the width of the value. And all implementations that do anything with
the data have an assert that `val.size() == wid`.

Remove the `wid` parameter from these functions and just use `val.size()`
directly where needed. This allows to simplify the interface and also
to remove the asserts.

Signed-off-by: Lars-Peter Clausen <[email protected]>
2022-05-28 15:34:02 +02:00

56 lines
1.8 KiB
C++

#ifndef IVL_bufif_H
#define IVL_bufif_H
/*
* Copyright (c) 2001-2016 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
# include "vvp_net.h"
/*
* The vvp_fun_bufif functor implements the logic of bufif0/1 and
* notif0/1 gates. Input 0 is the value to be buffered, and input 1 is
* the enable. The gate processes vectors as bit slices handled by an
* array of gates.
*
* The output from the gate is a vvp_vector8_t. The gate adds
* strengths to the buffered value, and sends H/L in response to
* unknown enable bits.
*/
class vvp_fun_bufif : public vvp_net_fun_t {
public:
vvp_fun_bufif(bool en_invert, bool out_invert,
unsigned str0, unsigned str1);
void recv_vec4(vvp_net_ptr_t port, const vvp_vector4_t&bit,
vvp_context_t);
void recv_vec4_pv(vvp_net_ptr_t ptr, const vvp_vector4_t&bit,
unsigned base, unsigned vwid, vvp_context_t ctx);
private:
vvp_vector4_t bit_;
vvp_vector4_t en_;
unsigned pol_ : 1;
unsigned inv_ : 1;
unsigned drive0_ : 8;
unsigned drive1_ : 8;
};
#endif /* IVL_bufif_H */