21 lines
335 B
Verilog
21 lines
335 B
Verilog
module test;
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wire w4;
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tri0 w8;
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wire real wr;
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reg failed = 0;
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initial begin
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#0;
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$display("w4 %b w8 %b wr %f", w4, w8, wr);
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if (w4 !== 1'b1) failed = 1;
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if (w8 !== 1'b1) failed = 1;
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if (wr != 1.0) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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