45 lines
680 B
Verilog
45 lines
680 B
Verilog
module test;
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logic [7:0] dout;
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logic [7:0] sel;
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for (genvar i = 0; i < 8; i++) begin
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if (i == 0) begin
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assign dout[i] = 1'b0;
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end else if (i == 1) begin
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assign dout[i] = 1'b1;
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end else begin
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// using always block reports error
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always @(*) begin
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if (sel[i]) dout[i] = 1'b1;
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else dout[i] = 1'b0;
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end
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end
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end
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logic [7:0] expected;
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reg failed = 0;
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initial begin
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sel = 8'd1;
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repeat (8) begin
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#1 $display("%b %b", sel, dout);
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expected = sel & 8'b11111100 | 8'b00000010;
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if (dout !== expected) failed = 1;
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sel = sel << 1;
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end
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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