22 lines
654 B
Verilog
22 lines
654 B
Verilog
// Strictly speaking this is illegal as it uses a hierarchical name in a
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// constant expression.
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module top;
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parameter ENABLE = 1;
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if (ENABLE) begin : blk
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wire [7:0] w;
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end
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wire [7:0] x;
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wire [$bits(blk.w)-1:0] y = 8'h55;
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wire [$bits(x)-1:0] z = 8'haa;
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initial begin
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$display("blk.w: %b (%0d bits)", blk.w, $bits(blk.w));
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$display("x: %b (%0d bits)", x, $bits(x));
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$display("y: %b (%0d bits)", y, $bits(y));
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$display("z: %b (%0d bits)", z, $bits(z));
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if (y === 8'h55 && z === 8'haa)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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