25 lines
352 B
Verilog
25 lines
352 B
Verilog
module test();
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typedef struct packed {
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logic [3:0] a;
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} inner_t;
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typedef struct packed {
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inner_t [1:0][3:0] fields;
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} outer_t;
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outer_t var1;
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outer_t var2;
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initial begin
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var1 = 32'h12345678;
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var2.fields = var1.fields;
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$display("%h", var2);
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if (var2 === 32'h12345678)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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