31 lines
998 B
Verilog
31 lines
998 B
Verilog
// The ternary operator should cause the 'in' variable to be unsigned extended.
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module test;
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reg passed;
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reg [7:0] res;
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reg signed in;
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initial begin
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passed = 1'b1;
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in = 1;
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$display("in4: %0d", in);
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res = 0 ? 1'h0 : in;
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$display("T0 = %d, %d", 0 ? 1'h0 : in, res); // These work
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case (0 ? 1'h0 : in) // But this fails
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5'b0101: begin $display("FAILED: T0 matched 5'b0101"); passed = 1'b0;end
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8'b000001: begin $display("T0 matched 8'b000001"); end
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default: begin $display("FAILED: T0 matched default"); passed = 1'b0;end
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endcase
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res = 1 ? in : 1'h0;
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$display("T1 = %d, %d", 1 ? in : 1'h0, res); // These work
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case (1 ? in : 1'h0) // But this fails
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5'b0101: begin $display("FAILED: T1 matched 5'b0101"); passed = 1'b0;end
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8'b000001: begin $display("T1 matched 8'b000001"); end
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default: begin $display("FAILED: T1 matched default"); passed = 1'b0;end
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endcase
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if (passed) $display("PASSED");
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end
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endmodule
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