26 lines
568 B
Verilog
26 lines
568 B
Verilog
module Foo #(parameter logic F = 1'b1) (input logic i = F);
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initial begin
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#1;
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$display("%m has an input value of %b.", i);
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if (i !== F) begin
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$display("FAILED: %m.i = %b ,expected %b!", i, F);
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Test.passed = 1'b0;
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end
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end
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endmodule
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module Test;
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reg passed;
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initial passed = 1'b1;
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// FIXME: A default value is not currently supported for
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// a module instance array.
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// defparam e[0].F = 1'b0;
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// Foo e[1:0]();
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defparam g.F = 1'b0;
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Foo f(), g();
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Foo #(.F(1'bz)) h();
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final if (passed) $display("PASSED");
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endmodule
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