11 lines
370 B
Verilog
11 lines
370 B
Verilog
module test;
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// This should conflict with the generate loops below.
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reg named;
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// scope name matches a register
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for (genvar gv = 0; gv < 1; gv = gv + 1) begin:named; end;
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// You cannot have generate blocks with the same name.
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for (genvar gv = 0; gv < 1; gv = gv + 1) begin:match; end;
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for (genvar gv = 0; gv < 1; gv = gv + 1) begin:match; end;
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endmodule
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