119 lines
2.4 KiB
Verilog
119 lines
2.4 KiB
Verilog
module top;
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reg passed;
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real inr, ctrl;
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wire out_nm, out_rnm, out_pm, out_rpm;
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wire out_cm_n, out_cm_p, out_rcm_n, out_rcm_p;
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pmos(out_pm, inr, ctrl);
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rpmos(out_rpm, inr, ctrl);
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nmos(out_nm, inr, 1'b1);
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rnmos(out_rnm, inr, 1'b1);
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cmos(out_cm_n, inr, 1'b1, 1'b1);
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cmos(out_cm_p, inr, ctrl, ctrl);
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cmos(out_rcm_n, inr, 1'b1, 1'b1);
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cmos(out_rcm_p, inr, ctrl, ctrl);
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always @(out_pm) begin
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int inr_int;
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inr_int = inr;
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if (out_pm !== inr_int[0]) begin
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$display("pmos of %f not equal to %b", inr, inr_int[0]);
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passed = 1'b0;
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end
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end
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always @(out_rpm) begin
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int inr_int;
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inr_int = inr;
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if (out_rpm !== inr_int[0]) begin
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$display("rpmos of %f not equal to %b", inr, inr_int[0]);
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passed = 1'b0;
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end
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end
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always @(out_nm) begin
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int inr_int;
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inr_int = inr;
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if (out_nm !== inr_int[0]) begin
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$display("nmos of %f not equal to %b", inr, inr_int[0]);
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passed = 1'b0;
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end
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end
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always @(out_rnm) begin
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int inr_int;
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inr_int = inr;
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if (out_rnm !== inr_int[0]) begin
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$display("rnmos of %f not equal to %b", inr, inr_int[0]);
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passed = 1'b0;
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end
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end
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always @(out_cm_n) begin
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int inr_int;
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inr_int = inr;
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if (out_cm_n !== inr_int[0]) begin
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$display("cmos(N) of %f not equal to %b", inr, inr_int[0]);
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passed = 1'b0;
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end
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end
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always @(out_cm_p) begin
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int inr_int;
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inr_int = inr;
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if (out_cm_p !== inr_int[0]) begin
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$display("cmos(P) of %f not equal to %b", inr, inr_int[0]);
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passed = 1'b0;
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end
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end
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always @(out_rcm_n) begin
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int inr_int;
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inr_int = inr;
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if (out_rcm_n !== inr_int[0]) begin
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$display("rcmos(N) of %f not equal to %b", inr, inr_int[0]);
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passed = 1'b0;
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end
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end
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always @(out_rcm_p) begin
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int inr_int;
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inr_int = inr;
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if (out_rcm_p !== inr_int[0]) begin
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$display("rcmos(P) of %f not equal to %b", inr, inr_int[0]);
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passed = 1'b0;
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end
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end
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initial begin
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$display("n rn p rp cn rcn cp rcp in");
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$monitor(out_nm,,,out_rnm,,,out_pm,,,out_rpm,,,out_cm_n,,,out_rcm_n,,,,out_cm_p,,,out_rcm_p,,,,inr);
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#1;
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if (passed === 1'bx) passed = 1'b1;
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ctrl = 2.49;
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inr = 1.0;
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#1;
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inr = 0.0;
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#1
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inr = 3.0;
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#1;
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inr = 2.0;
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#1;
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inr = 4.0;
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#1;
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inr = 2.5;
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#1;
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inr = 2.49;
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#1;
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inr = -1.0;
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#1;
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inr = 1.0/0.0;
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#1;
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if (passed) $display("PASSED");
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end
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endmodule
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