77 lines
1.4 KiB
Verilog
77 lines
1.4 KiB
Verilog
module top;
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reg passed;
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real inr, ctrl;
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wire out_bf0, out_bf1, out_nt0, out_nt1;
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bufif0(out_bf0, inr, ctrl);
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bufif1(out_bf1, inr, 1'b1);
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notif0(out_nt0, inr, ctrl);
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notif1(out_nt1, inr, 1'b1);
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always @(out_bf0) begin
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int inr_int;
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inr_int = inr;
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if (out_bf0 !== inr_int[0]) begin
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$display("bufif0 of %f not equal to %b", inr, inr_int[0]);
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passed = 1'b0;
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end
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end
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always @(out_bf1) begin
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int inr_int;
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inr_int = inr;
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if (out_bf1 !== inr_int[0]) begin
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$display("bufif1 of %f not equal to %b", inr, inr_int[0]);
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passed = 1'b0;
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end
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end
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always @(out_nt0) begin
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int inr_int;
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inr_int = inr;
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if (out_nt0 !== !inr_int[0]) begin
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$display("bufif0 of %f not equal to %b", inr, !inr_int[0]);
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passed = 1'b0;
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end
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end
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always @(out_nt1) begin
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int inr_int;
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inr_int = inr;
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if (out_nt1 !== !inr_int[0]) begin
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$display("bufif1 of %f not equal to %b", inr, !inr_int[0]);
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passed = 1'b0;
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end
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end
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initial begin
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$display("b0 b1 n0 n1 in");
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$monitor(out_bf0,,,out_bf1,,,out_nt0,,,out_nt1,,,inr);
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#1;
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if (passed === 1'bx) passed = 1'b1;
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ctrl = 2.49;
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inr = 1.0;
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#1;
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inr = 0.0;
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#1
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inr = 3.0;
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#1;
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inr = 2.0;
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#1;
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inr = 4.0;
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#1;
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inr = 2.5;
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#1;
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inr = 2.49;
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#1;
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inr = -1.0;
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#1;
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inr = 1.0/0.0;
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#1;
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if (passed) $display("PASSED");
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end
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endmodule
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