116 lines
2.3 KiB
Verilog
116 lines
2.3 KiB
Verilog
module top;
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reg passed;
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real inr;
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wire out_buf, out_not, out_and, out_nand, out_or, out_nor, out_xor, out_xnor;
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buf(out_buf, inr);
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not(out_not, inr);
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and(out_and, inr, 1'b1);
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nand(out_nand, inr, 1'b1);
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or(out_or, inr, 1'b0);
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nor(out_nor, inr, 1'b0);
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xor(out_xor, inr, 1'b1);
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xnor(out_xnor, inr, 1'b1);
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always @(out_not) begin
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int inr_int;
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inr_int = inr;
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if (out_not !== !inr_int[0]) begin
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$display("not of %f not equal to %b", inr, !inr_int[0]);
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passed = 1'b0;
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end
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end
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always @(out_buf) begin
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int inr_int;
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inr_int = inr;
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if (out_buf !== inr_int[0]) begin
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$display("buf of %f not equal to %b", inr, inr_int[0]);
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passed = 1'b0;
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end
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end
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always @(out_and) begin
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int inr_int;
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inr_int = inr;
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if (out_and !== inr_int[0]) begin
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$display("and of %f not equal to %b", inr, inr_int[0]);
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passed = 1'b0;
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end
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end
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always @(out_nand) begin
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int inr_int;
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inr_int = inr;
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if (out_nand !== !inr_int[0]) begin
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$display("nand of %f not equal to %b", inr, !inr_int[0]);
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passed = 1'b0;
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end
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end
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always @(out_or) begin
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int inr_int;
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inr_int = inr;
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if (out_or !== inr_int[0]) begin
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$display("or of %f not equal to %b", inr, inr_int[0]);
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passed = 1'b0;
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end
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end
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always @(out_nor) begin
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int inr_int;
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inr_int = inr;
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if (out_nor !== !inr_int[0]) begin
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$display("nor of %f not equal to %b", inr, !inr_int[0]);
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passed = 1'b0;
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end
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end
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always @(out_xor) begin
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int inr_int;
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inr_int = inr;
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if (out_xor !== !inr_int[0]) begin
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$display("xor of %f not equal to %b", inr, !inr_int[0]);
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passed = 1'b0;
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end
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end
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always @(out_xnor) begin
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int inr_int;
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inr_int = inr;
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if (out_xnor !== inr_int[0]) begin
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$display("xnor of %f not equal to %b", inr, inr_int[0]);
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passed = 1'b0;
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end
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end
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initial begin
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$display("bf nt an na or no xo xn in");
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$monitor(out_buf,,,out_not,,,out_and,,,out_nand,,,out_or,,,out_nor,,,out_xor,,,out_xnor,,,inr);
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#1;
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if (passed === 1'bx) passed = 1'b1;
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inr = 1.0;
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#1;
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inr = 0.0;
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#1
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inr = 3.0;
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#1;
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inr = 2.0;
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#1;
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inr = 4.0;
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#1;
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inr = 2.5;
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#1;
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inr = 2.49;
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#1;
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inr = -1.0;
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#1;
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inr = 1.0/0.0;
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#1;
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if (passed) $display("PASSED");
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end
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endmodule
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