28 lines
997 B
Verilog
28 lines
997 B
Verilog
module top;
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real rout_ca1, rout_ca2, rout_valid, rout_gt, rout_udp;
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logic lout_ca1, lout_ca2, lout_valid1, lout_valid2, lout_gt, lout_udp;
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reg in;
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assign (weak1, weak0) {rout_ca1, rout_ca2} = in; // Non-default strength so invalid
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assign (weak1, weak0) {lout_ca1, lout_ca2} = in; // Non-default strength so invalid
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assign (strong1, strong0) rout_valid = in; // Ok, real cannot be in a concatenation
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assign (strong1, strong0) {lout_valid1, lout_valid2} = in; // Ok, default strength
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and (rout_gt, in, in); // Gates must drive a net
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and (lout_gt, in, in); // Gates must drive a net
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// When strength is added it should only be for the default strength!
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udp_inv (rout_udp, in); // A UDP is like a module and can drive a variable
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udp_inv (lout_udp, in); // A UDP is like a module and can drive a variable
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initial $display("FAILED: There should be compile errors!");
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endmodule
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primitive udp_inv (output y, input a);
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table
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0 : 1;
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1 : 0;
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endtable
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endprimitive
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