43 lines
919 B
Verilog
43 lines
919 B
Verilog
module net_connect #(parameter WIDTH=1) (wo, w);
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output wire[WIDTH-1:0] wo;
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input wire[WIDTH-1:0] w;
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assign wo = w;
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endmodule
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module ReplicateMod (
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input wire [3:0] bus,
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output wire [7:0] replicated
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);
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net_connect #(.WIDTH(8)) net_connect (replicated, ({2{bus}}));
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endmodule
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module tb;
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logic passed;
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logic [3:0] bus;
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wire [7:0] replicated;
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wire [3:0] wire__bus = bus;
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ReplicateMod dut(.bus(wire__bus), .replicated(replicated));
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initial begin
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passed = 1'b1;
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bus = 4'h3;
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#1
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if(replicated !== 8'h33) begin
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passed = 1'b0;
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$display("FAILED: Expected 'h33, but found 'h%x with inputs 'h%x", replicated, bus);
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end
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#1
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bus = 4'hc;
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#1
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if(replicated !== 8'hcc) begin
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passed = 1'b0;
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$display("FAILED: Expected 'hcc, but found 'h%x with inputs 'h%x", replicated, bus);
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end
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#1
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if (passed) $display("PASSED");
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end
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endmodule
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