30 lines
736 B
Verilog
30 lines
736 B
Verilog
module module_0 #(
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parameter id_1 = 32'd92,
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parameter id_3 = 32'd50,
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parameter id_4 = 32'd25,
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parameter id_8 = 32'd99,
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parameter id_9 = 32'd40
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) ();
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// Was this intended to be a generate case or procedural case?
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case ((1))
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1: begin
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if (id_3) begin
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// else with no if or missing end.
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else begin
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end else begin
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if (1)
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// This is parsed as a generate case so no procedural
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// assignment is allowed. Plus you cannot assign
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// to a parameter.
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id_3 = id_9[1];
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end
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// This is the closing for the begin above, but the
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// else likely broke the sequence. So there is now
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// an extra end.
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end
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end
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endcase
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endmodule
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