25 lines
625 B
Verilog
25 lines
625 B
Verilog
`define check(expr) \
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result = expr; \
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$display("%b", result); \
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if (result !== 32'b11111111111111111111111111011111) failed = 1;
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module top;
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integer x;
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localparam Y = 1'sb1;
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localparam integer Z = 1'sb1;
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reg [31:0] result;
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reg failed = 0;
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initial begin
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`check($bits(x) ^ 1'sb1);
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`check($bits(x) ^ Y);
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`check($bits(x) ^ Z);
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`check($signed($bits(x)) ^ 1'sb1);
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`check($signed($bits(x)) ^ Y);
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`check($signed($bits(x)) ^ Z);
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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