35 lines
851 B
Verilog
35 lines
851 B
Verilog
module test;
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// The test is sensitive to the order in which the code is generated for
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// the individual assignments, which currently depends on the alphabetic
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// order of the array names. So duplicate the test with the order reversed
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// to protect against future compiler changes.
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wire [7:0] array1[0:1];
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wire [7:0] array2[0:0];
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assign array2[0] = 8'h55;
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assign array1[0] = { array2[0] };
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assign array1[1] = { array2[0] };
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wire [7:0] array3[0:0];
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wire [7:0] array4[0:1];
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assign array3[0] = 8'haa;
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assign array4[0] = { array3[0] };
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assign array4[1] = { array3[0] };
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initial begin
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#0 $display("%h %h", array1[0], array1[1]);
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#0 $display("%h %h", array4[0], array4[1]);
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if (array1[0] === 8'h55 && array1[1] === 8'h55 &&
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array4[0] === 8'haa && array4[1] === 8'haa)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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