19 lines
618 B
Verilog
19 lines
618 B
Verilog
module test_mod ();
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typedef enum logic [4:0] {ENUM_ELEM1, ENUM_ELEM2} test_enum_t;
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test_enum_t test_mem_addr_e;
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logic [1:0] test_mem [test_mem_addr_e.num()];
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initial begin
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test_mem[ENUM_ELEM1] = 1;
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test_mem[ENUM_ELEM2] = 2;
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$display("ENUM_ELEM1 = %d test_mem[ENUM_ELEM1] = %d", ENUM_ELEM1, test_mem[ENUM_ELEM1]);
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$display("ENUM_ELEM2 = %d test_mem[ENUM_ELEM2] = %d", ENUM_ELEM2, test_mem[ENUM_ELEM2]);
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if (test_mem[ENUM_ELEM1] === 1 && test_mem[ENUM_ELEM2] === 2)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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