23 lines
307 B
Verilog
23 lines
307 B
Verilog
module dut(output logic [7:0] op[1:0]);
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assign op[0] = 8'd1;
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assign op[1] = 8'd2;
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endmodule
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module test();
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logic [7:0] v[1:0];
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dut dut(v);
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initial begin
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#0 $display("%b %b", v[0], v[1]);
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if ((v[0] === 8'd1) && (v[1] === 8'd2))
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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