573 lines
14 KiB
C
573 lines
14 KiB
C
/*
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* Copyright (c) 2003-2013 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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/*
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* This file includes functions for evaluating REAL expressions.
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*/
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# include "vvp_priv.h"
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# include <string.h>
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# include <stdlib.h>
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# include <math.h>
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# include <assert.h>
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# include <stdbool.h>
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static unsigned long word_alloc_mask = 0x0f;
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int allocate_word()
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{
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int res = 4;
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int max = WORD_COUNT;
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while (res < max && (1U << res) & word_alloc_mask)
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res += 1;
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if (res >= max) {
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fprintf(stderr, "vvp.tgt error: Thread words exhausted.\n");
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exit(1);
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}
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word_alloc_mask |= 1U << res;
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return res;
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}
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void clr_word(int res)
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{
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int max = WORD_COUNT;
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assert(res < max);
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word_alloc_mask &= ~ (1U << res);
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}
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static void draw_binary_real(ivl_expr_t expr)
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{
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switch (ivl_expr_opcode(expr)) {
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case 'E':
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case 'N':
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case 'l':
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case 'r':
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case 'R':
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case '&':
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case '|':
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case '^':
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case 'A':
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case 'O':
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case 'X':
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/* These should be caught in draw_eval_real(). */
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assert(0);
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}
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draw_eval_real(ivl_expr_oper1(expr));
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draw_eval_real(ivl_expr_oper2(expr));
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switch (ivl_expr_opcode(expr)) {
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case '+':
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fprintf(vvp_out, " %%add/wr;\n");
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break;
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case '-':
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fprintf(vvp_out, " %%sub/wr;\n");
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break;
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case '*':
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fprintf(vvp_out, " %%mul/wr;\n");
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break;
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case '/':
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fprintf(vvp_out, " %%div/wr;\n");
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break;
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case '%':
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fprintf(vvp_out, " %%mod/wr;\n");
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break;
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case 'p':
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fprintf(vvp_out, " %%pow/wr;\n");
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break;
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case 'm':
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fprintf(vvp_out, " %%min/wr;\n");
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break;
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case 'M':
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fprintf(vvp_out, " %%max/wr;\n");
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break;
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default:
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fprintf(stderr, "XXXX draw_binary_real(%c)\n",
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ivl_expr_opcode(expr));
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assert(0);
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}
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}
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static void draw_number_real(ivl_expr_t expr)
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{
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unsigned int idx;
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const char*bits = ivl_expr_bits(expr);
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unsigned wid = ivl_expr_width(expr);
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unsigned long mant = 0;
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int vexp = 0x1000;
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/* If this is a negative number, then arrange for the 2's
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complement to be calculated as we scan through the
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value. Real values are sign-magnitude, and this negation
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gets us a magnitude. */
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int negate = 0;
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int carry = 0;
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if (ivl_expr_signed(expr) && (bits[wid-1] == '1')) {
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negate = 1;
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carry = 1;
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}
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for (idx = 0 ; idx < wid && idx < IMM_WID ; idx += 1) {
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int cur_bit = bits[idx] == '1'? 1 : 0;
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if (negate) {
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cur_bit ^= 1;
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cur_bit += carry;
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carry = (cur_bit >> 1) & 1;
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cur_bit &= 1;
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}
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if (cur_bit) mant |= 1 << idx;
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}
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for ( ; idx < wid ; idx += 1) {
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if (ivl_expr_signed(expr) && (bits[idx] == bits[IMM_WID-1]))
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continue;
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if (bits[idx] == '0')
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continue;
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fprintf(stderr, "vvp.tgt error: mantissa doesn't fit!\n");
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assert(0);
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}
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/* If required, add in a sign bit. */
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if (negate)
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vexp |= 0x4000;
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fprintf(vvp_out, " %%pushi/real %lu, %d; load(num)= %c%lu (wid=%u)\n",
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mant, vexp, (vexp&0x4000)? '-' : '+', mant, wid);
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}
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static void draw_property_real(ivl_expr_t expr)
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{
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ivl_signal_t sig = ivl_expr_signal(expr);
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unsigned pidx = ivl_expr_property_idx(expr);
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fprintf(vvp_out, " %%load/obj v%p_0;\n", sig);
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fprintf(vvp_out, " %%prop/r %u;\n", pidx);
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}
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static void draw_realnum_real(ivl_expr_t expr)
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{
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double value = ivl_expr_dvalue(expr);
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double fract;
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int expo, vexp;
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unsigned long mant;
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int sign = 0;
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/* Handle the special case that the value is +-inf. */
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if (isinf(value)) {
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if (value > 0)
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fprintf(vvp_out, " %%pushi/real 0, %d; load=+inf\n",
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0x3fff);
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else
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fprintf(vvp_out, " %%pushi/real 0, %d; load=-inf\n",
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0x7fff);
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return;
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}
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/* Handle the special case that the value is NaN. */
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if (value != value) {
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fprintf(vvp_out, " %%pushi/real 1, %d; load=NaN\n",
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0x3fff);
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return;
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}
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if (value < 0) {
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sign = 0x4000;
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value *= -1;
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}
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fract = frexp(value, &expo);
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fract = ldexp(fract, 31);
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mant = fract;
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expo -= 31;
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vexp = expo + 0x1000;
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assert(vexp >= 0);
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assert(vexp < 0x2000);
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vexp += sign;
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fprintf(vvp_out, " %%pushi/real %lu, %d; load=%#g\n",
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mant, vexp, ivl_expr_dvalue(expr));
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/* Capture the residual bits, if there are any. Note that an
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IEEE754 mantissa has 52 bits, 31 of which were accounted
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for already. */
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fract -= floor(fract);
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fract = ldexp(fract, 22);
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mant = fract;
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expo -= 22;
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vexp = expo + 0x1000;
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assert(vexp >= 0);
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assert(vexp < 0x2000);
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vexp += sign;
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if (mant != 0) {
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fprintf(vvp_out, " %%pushi/real %lu, %d; load=%#g\n",
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mant, vexp, ivl_expr_dvalue(expr));
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fprintf(vvp_out, " %%add/wr;\n");
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}
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}
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/*
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* The real value of a logic expression is the integer value of the
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* expression converted to real.
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*/
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static void draw_real_logic_expr(ivl_expr_t expr, int stuff_ok_flag)
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{
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struct vector_info sv = draw_eval_expr(expr, stuff_ok_flag);
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const char*sign_flag = ivl_expr_signed(expr)? "/s" : "";
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if (sv.wid > 64) {
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fprintf(vvp_out, " %%cvt/rv%s %u, %u;\n",
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sign_flag, sv.base, sv.wid);
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} else {
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int res = allocate_word();
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fprintf(vvp_out, " %%ix/get%s %d, %u, %u;\n",
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sign_flag, res, sv.base, sv.wid);
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if (ivl_expr_signed(expr))
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fprintf(vvp_out, " %%cvt/rs %d;\n", res);
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else
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fprintf(vvp_out, " %%cvt/ru %d;\n", res);
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clr_word(res);
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}
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clr_vector(sv);
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}
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static void draw_select_real(ivl_expr_t expr)
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{
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/* The sube references the expression to be selected from. */
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ivl_expr_t sube = ivl_expr_oper1(expr);
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/* This is the select expression */
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ivl_expr_t shift= ivl_expr_oper2(expr);
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/* Assume the sub-expression is a signal */
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ivl_signal_t sig = ivl_expr_signal(sube);
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assert(ivl_signal_data_type(sig) == IVL_VT_DARRAY);
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draw_eval_expr_into_integer(shift, 3);
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fprintf(vvp_out, " %%load/dar/r v%p_0;\n", sig);
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}
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static void draw_sfunc_real(ivl_expr_t expr)
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{
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switch (ivl_expr_value(expr)) {
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case IVL_VT_REAL:
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if (ivl_expr_parms(expr) == 0) {
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fprintf(vvp_out, " %%vpi_func/r %u %u \"%s\" {0 0};\n",
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ivl_file_table_index(ivl_expr_file(expr)),
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ivl_expr_lineno(expr), ivl_expr_name(expr));
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} else {
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draw_vpi_rfunc_call(expr);
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}
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break;
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case IVL_VT_VECTOR:
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/* If the value of the sfunc is a vector, then evaluate
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it as a vector, then convert the result to a real
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(via an index register) for the result. */
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draw_real_logic_expr(expr, 0);
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break;
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default:
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assert(0);
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}
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}
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static void draw_signal_real_real(ivl_expr_t expr)
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{
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ivl_signal_t sig = ivl_expr_signal(expr);
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if (ivl_signal_dimensions(sig) == 0) {
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fprintf(vvp_out, " %%load/real v%p_0;\n", sig);
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return;
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}
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ivl_expr_t word_ex = ivl_expr_oper1(expr);
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int word_ix = allocate_word();
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draw_eval_expr_into_integer(word_ex, word_ix);
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fprintf(vvp_out, " %%load/ar v%p, %d;\n", sig, word_ix);
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clr_word(word_ix);
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}
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static void draw_signal_real(ivl_expr_t expr)
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{
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ivl_signal_t sig = ivl_expr_signal(expr);
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switch (ivl_signal_data_type(sig)) {
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case IVL_VT_LOGIC:
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draw_real_logic_expr(expr, 0);
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return;
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case IVL_VT_REAL:
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draw_signal_real_real(expr);
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return;
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default:
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fprintf(stderr, "vvp.tgt error: signal_data_type=%d\n",
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ivl_signal_data_type(sig));
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assert(0);
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return;
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}
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}
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/* If we have nested ternary operators they are likely tail recursive.
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* This code is structured to allow this recursion without overflowing
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* the available thread words. */
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static void draw_ternary_real(ivl_expr_t expr)
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{
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ivl_expr_t cond = ivl_expr_oper1(expr);
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ivl_expr_t true_ex = ivl_expr_oper2(expr);
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ivl_expr_t false_ex = ivl_expr_oper3(expr);
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struct vector_info tst;
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unsigned lab_true = local_count++;
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unsigned lab_out = local_count++;
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/* Evaluate the ternary condition. */
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tst = draw_eval_expr(cond, STUFF_OK_XZ|STUFF_OK_RO);
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if ((tst.base >= 4) && (tst.wid > 1)) {
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struct vector_info tmp;
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fprintf(vvp_out, " %%or/r %u, %u, %u;\n",
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tst.base, tst.base, tst.wid);
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tmp = tst;
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tmp.base += 1;
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tmp.wid -= 1;
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clr_vector(tmp);
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tst.wid = 1;
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}
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/* Evaluate the true expression second. */
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fprintf(vvp_out, " %%jmp/1 T_%u.%u, %u;\n",
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thread_count, lab_true, tst.base);
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/* Evaluate the false expression. */
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draw_eval_real(false_ex);
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fprintf(vvp_out, " %%jmp/0 T_%u.%u, %u; End of false expr.\n",
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thread_count, lab_out, tst.base);
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/* If the conditional is undefined then blend the real words. */
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draw_eval_real(true_ex);
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fprintf(vvp_out, " %%blend/wr;\n");
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fprintf(vvp_out, " %%jmp T_%u.%u; End of blend\n",
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thread_count, lab_out);
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/* Evaluate the true expression. */
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fprintf(vvp_out, "T_%u.%u ;\n", thread_count, lab_true);
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draw_eval_real(true_ex);
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/* This is the out label. */
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fprintf(vvp_out, "T_%u.%u ;\n", thread_count, lab_out);
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clr_vector(tst);
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}
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static void increment(ivl_expr_t e, bool pre)
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{
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ivl_signal_t sig = ivl_expr_signal(e);
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fprintf(vvp_out, " %%load/real v%p_0;\n", sig);
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if (!pre) fprintf(vvp_out, " %%dup/real;\n");
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fprintf(vvp_out, " %%pushi/real 1, 0x1000;\n");
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fprintf(vvp_out, " %%add/wr;\n");
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if ( pre) fprintf(vvp_out, " %%dup/real;\n");
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fprintf(vvp_out, " %%store/real v%p_0;\n", sig);
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}
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static void decrement(ivl_expr_t e, bool pre)
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{
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ivl_signal_t sig = ivl_expr_signal(e);
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fprintf(vvp_out, " %%load/real v%p_0;\n", sig);
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if (!pre) fprintf(vvp_out, " %%dup/real;\n");
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fprintf(vvp_out, " %%pushi/real 1, 0x1000;\n");
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fprintf(vvp_out, " %%sub/wr;\n");
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if ( pre) fprintf(vvp_out, " %%dup/real;\n");
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fprintf(vvp_out, " %%store/real v%p_0;\n", sig);
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}
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static void draw_unary_real(ivl_expr_t expr)
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{
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ivl_expr_t sube;
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/* If the opcode is a ~ or a ! then the sub expression must not be
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* a real expression, so use vector evaluation and then convert
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* that result to a real value. */
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if ((ivl_expr_opcode(expr) == '~') || (ivl_expr_opcode(expr) == '!')) {
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draw_real_logic_expr(expr, STUFF_OK_XZ);
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return;
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}
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sube = ivl_expr_oper1(expr);
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if (ivl_expr_opcode(expr) == 'r') { /* Cast an integer value to a real. */
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struct vector_info res;
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const char *suffix = "";
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assert(ivl_expr_value(sube) != IVL_VT_REAL);
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res = draw_eval_expr(sube, 1);
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if (ivl_expr_signed(sube)) suffix = "/s";
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fprintf(vvp_out, " %%cvt/rv%s %u, %u;\n", suffix, res.base, res.wid);
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clr_vector(res);
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return;
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}
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if (ivl_expr_opcode(expr) == '+') {
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draw_eval_real(sube);
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return;
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}
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if (ivl_expr_opcode(expr) == '-') {
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fprintf(vvp_out, " %%pushi/real 0, 0; load 0.0\n");
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draw_eval_real(sube);
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fprintf(vvp_out, " %%sub/wr;\n");
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return;
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}
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if (ivl_expr_opcode(expr) == 'm') { /* abs() */
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draw_eval_real(sube);
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fprintf(vvp_out, " %%abs/wr;\n");
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return;
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}
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if (ivl_expr_opcode(expr) == 'v') { /* Handled in eval_expr.c. */
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fprintf(stderr, "vvp.tgt error: real -> integer cast in real "
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"context.\n");
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assert(0);
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}
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switch (ivl_expr_opcode(expr)) {
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case 'I':
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increment(sube, true);
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return;
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case 'i':
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increment(sube, false);
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return;
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case 'D':
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decrement(sube, true);
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return;
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case 'd':
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decrement(sube, false);
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return;
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}
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fprintf(stderr, "vvp.tgt error: unhandled real unary operator: %c.\n",
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ivl_expr_opcode(expr));
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assert(0);
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}
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void draw_eval_real(ivl_expr_t expr)
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{
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/* If this expression/sub-expression is not real then we need
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* to evaluate it as a bit value and then convert the bit based
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* result to a real value. This is required to get integer
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* division to work correctly. */
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if (ivl_expr_value(expr) != IVL_VT_REAL) {
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draw_real_logic_expr(expr, STUFF_OK_XZ);
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return;
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}
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switch (ivl_expr_type(expr)) {
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case IVL_EX_BINARY:
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draw_binary_real(expr);
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break;
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case IVL_EX_NUMBER:
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draw_number_real(expr);
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break;
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case IVL_EX_PROPERTY:
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draw_property_real(expr);
|
|
break;
|
|
|
|
case IVL_EX_REALNUM:
|
|
draw_realnum_real(expr);
|
|
break;
|
|
|
|
case IVL_EX_SELECT:
|
|
draw_select_real(expr);
|
|
break;
|
|
|
|
case IVL_EX_SFUNC:
|
|
draw_sfunc_real(expr);
|
|
break;
|
|
|
|
case IVL_EX_SIGNAL:
|
|
draw_signal_real(expr);
|
|
break;
|
|
|
|
case IVL_EX_TERNARY:
|
|
draw_ternary_real(expr);
|
|
break;
|
|
|
|
case IVL_EX_UFUNC:
|
|
draw_ufunc_real(expr);
|
|
break;
|
|
|
|
case IVL_EX_UNARY:
|
|
draw_unary_real(expr);
|
|
break;
|
|
|
|
default:
|
|
if (ivl_expr_value(expr) == IVL_VT_VECTOR) {
|
|
struct vector_info sv = draw_eval_expr(expr, 0);
|
|
const char*sign_flag = ivl_expr_signed(expr)? "/s" : "";
|
|
|
|
clr_vector(sv);
|
|
int res = allocate_word();
|
|
|
|
fprintf(vvp_out, " %%ix/get%s %d, %u, %u;\n",
|
|
sign_flag, res, sv.base, sv.wid);
|
|
|
|
fprintf(vvp_out, " %%cvt/rs %d;\n", res);
|
|
|
|
clr_word(res);
|
|
|
|
} else {
|
|
fprintf(stderr, "XXXX Evaluate real expression (%d)\n",
|
|
ivl_expr_type(expr));
|
|
fprintf(vvp_out, " ; XXXX Evaluate real expression (%d)\n",
|
|
ivl_expr_type(expr));
|
|
return;
|
|
}
|
|
break;
|
|
}
|
|
|
|
}
|