515 lines
13 KiB
C
515 lines
13 KiB
C
/*
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* Copyright (c) 2000 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: verilog.c,v 1.29 2007/02/26 19:49:50 steve Exp $"
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#endif
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# include "config.h"
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/*
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* This target writes a Verilog description of the design. The output
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* Verilog is a single module that has the name of the root module of
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* the design, but is internally the complete design.
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*/
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# include "ivl_target.h"
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# include <stdio.h>
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# include <assert.h>
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/* This is the output file where the Verilog program is sent. */
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static FILE*out;
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/*
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* Scoped objects are the signals, reg and wire and what-not. What
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* this function does is draw the objects of the scope, along with a
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* fake scope context so that the hierarchical name remains
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* pertinent.
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*/
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static void draw_scoped_objects(ivl_design_t des)
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{
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ivl_scope_t root = ivl_design_root(des);
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unsigned cnt, idx;
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cnt = ivl_scope_sigs(root);
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for (idx = 0 ; idx < cnt ; idx += 1) {
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ivl_signal_t sig = ivl_scope_sig(root, idx);
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switch (ivl_signal_type(sig)) {
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case IVL_SIT_REG:
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if (ivl_signal_pins(sig) > 1)
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fprintf(out, " reg [%u:0] %s;\n",
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ivl_signal_pins(sig),
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ivl_signal_basename(sig));
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else
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fprintf(out, " reg %s;\n",
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ivl_signal_basename(sig));
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break;
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case IVL_SIT_TRI:
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fprintf(out, " wire %s;\n", ivl_signal_basename(sig));
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break;
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default:
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assert(0);
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}
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}
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}
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/*
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* Given a nexus, this function draws a signal reference. We don't
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* care really whether the signal is a reg or wire, because this may
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* be an input or output of a gate. Just print it. And if this is a
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* bit of a vector, draw the bit select needed to get at the right bit.
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*/
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static void draw_nexus(ivl_nexus_t nex)
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{
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ivl_signal_t sig=NULL;
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ivl_nexus_ptr_t ptr=NULL;
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unsigned idx;
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for (idx = 0 ; idx < ivl_nexus_ptrs(nex) ; idx += 1) {
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ptr = ivl_nexus_ptr(nex, idx);
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sig = ivl_nexus_ptr_sig(ptr);
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if (sig)
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break;
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}
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assert(sig);
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if (ivl_signal_pins(sig) == 1) {
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fprintf(out, "%s", ivl_signal_name(sig));
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} else {
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fprintf(out, "%s[%u]", ivl_signal_name(sig),
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ivl_nexus_ptr_pin(ptr));
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}
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}
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/*
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* Draw a single logic gate. Escape the name so that it is preserved
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* completely. This drawing is happening in the root scope so signal
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* references can remain hierarchical.
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*/
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static int draw_logic(ivl_net_logic_t net)
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{
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unsigned npins, idx;
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const char*name = ivl_logic_name(net);
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switch (ivl_logic_type(net)) {
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case IVL_LO_AND:
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fprintf(out, " and \\%s (", name);
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break;
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case IVL_LO_BUF:
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fprintf(out, " buf \\%s (", name);
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break;
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case IVL_LO_OR:
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fprintf(out, " or \\%s (", name);
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break;
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case IVL_LO_XOR:
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fprintf(out, " xor \\%s (", name);
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break;
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default:
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fprintf(out, "STUB: %s: unsupported gate\n", name);
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return -1;
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}
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draw_nexus(ivl_logic_pin(net, 0));
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npins = ivl_logic_pins(net);
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for (idx = 1 ; idx < npins ; idx += 1) {
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fprintf(out, ", ");
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draw_nexus(ivl_logic_pin(net,idx));
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}
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fprintf(out, ");\n");
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return 0;
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}
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/*
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* Scan the scope and its children for logic gates. Use the draw_logic
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* function to draw the actual gate.
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*/
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static int draw_scope_logic(ivl_scope_t scope, void*x)
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{
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unsigned cnt = ivl_scope_logs(scope);
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unsigned idx;
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for (idx = 0 ; idx < cnt ; idx += 1) {
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draw_logic(ivl_scope_log(scope, idx));
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}
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ivl_scope_children(scope, draw_scope_logic, 0);
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return 0;
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}
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static void show_expression(ivl_expr_t net)
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{
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if (net == 0)
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return;
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switch (ivl_expr_type(net)) {
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case IVL_EX_BINARY: {
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char code = ivl_expr_opcode(net);
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show_expression(ivl_expr_oper1(net));
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switch (code) {
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case 'e':
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fprintf(out, "==");
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break;
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case 'n':
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fprintf(out, "!=");
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break;
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case 'N':
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fprintf(out, "!==");
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break;
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case 'r':
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fprintf(out, ">>");
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break;
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default:
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fprintf(out, "%c", code);
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}
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show_expression(ivl_expr_oper2(net));
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break;
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}
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case IVL_EX_CONCAT: {
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unsigned idx;
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fprintf(out, "{");
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show_expression(ivl_expr_parm(net, 0));
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for (idx = 1 ; idx < ivl_expr_parms(net) ; idx += 1) {
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fprintf(out, ", ");
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show_expression(ivl_expr_parm(net, idx));
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}
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fprintf(out, "}");
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break;
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}
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case IVL_EX_NUMBER: {
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int sigflag = ivl_expr_signed(net);
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unsigned idx, width = ivl_expr_width(net);
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const char*bits = ivl_expr_bits(net);
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fprintf(out, "%u'%sb", width, sigflag? "s" : "");
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for (idx = width ; idx > 0 ; idx -= 1)
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fprintf(out, "%c", bits[idx-1]);
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break;
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}
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case IVL_EX_SFUNC:
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fprintf(out, "%s", ivl_expr_name(net));
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break;
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case IVL_EX_STRING:
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fprintf(out, "\"%s\"", ivl_expr_string(net));
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break;
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case IVL_EX_SIGNAL:
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fprintf(out, "%s", ivl_expr_name(net));
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break;
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default:
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fprintf(out, "...");
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}
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}
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/*
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* An assignment is one of a possible list of l-values to a behavioral
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* assignment. Each l-value is either a part select of a signal or a
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* non-constant bit select.
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*/
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static void show_assign_lval(ivl_lval_t lval)
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{
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ivl_nexus_t nex;
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ivl_nexus_ptr_t ptr;
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ivl_signal_t sig=NULL;
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unsigned idx;
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unsigned lsb=0;
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assert(ivl_lval_mux(lval) == 0);
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assert(ivl_lval_mem(lval) == 0);
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nex = ivl_lval_pin(lval, 0);
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for (idx = 0 ; idx < ivl_nexus_ptrs(nex) ; idx += 1) {
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unsigned pin;
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ptr = ivl_nexus_ptr(nex, idx);
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sig = ivl_nexus_ptr_sig(ptr);
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if (sig == 0)
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continue;
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lsb = ivl_nexus_ptr_pin(ptr);
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for (pin = 1 ; pin < ivl_lval_pins(lval) ; pin += 1) {
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if (ivl_signal_pin(sig, lsb+pin) != ivl_lval_pin(lval,pin))
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break;
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}
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if (pin < ivl_lval_pins(lval))
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continue;
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break;
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}
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assert(sig);
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if ((lsb > 0) || (lsb + ivl_lval_pins(lval)) < ivl_signal_pins(sig)) {
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fprintf(out, "%s[%u:%u]", ivl_signal_name(sig),
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lsb+ivl_lval_pins(lval)-1, lsb);
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} else {
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fprintf(out, "%s", ivl_signal_name(sig));
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}
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}
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static void show_assign_lvals(ivl_statement_t net)
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{
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const unsigned cnt = ivl_stmt_lvals(net);
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if (cnt == 1) {
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show_assign_lval(ivl_stmt_lval(net, 0));
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} else {
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unsigned idx;
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fprintf(out, "{");
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show_assign_lval(ivl_stmt_lval(net, 0));
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for (idx = 1 ; idx < cnt ; idx += 1) {
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fprintf(out, ", ");
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show_assign_lval(ivl_stmt_lval(net, idx));
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}
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fprintf(out, "}");
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}
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}
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static void show_statement(ivl_statement_t net, unsigned ind)
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{
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const ivl_statement_type_t code = ivl_statement_type(net);
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switch (code) {
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case IVL_ST_ASSIGN:
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fprintf(out, "%*s", ind, "");
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show_assign_lvals(net);
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fprintf(out, " = ");
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show_expression(ivl_stmt_rval(net));
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fprintf(out, ";\n");
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break;
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case IVL_ST_BLOCK: {
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unsigned cnt = ivl_stmt_block_count(net);
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unsigned idx;
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fprintf(out, "%*sbegin\n", ind, "");
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for (idx = 0 ; idx < cnt ; idx += 1) {
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ivl_statement_t cur = ivl_stmt_block_stmt(net, idx);
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show_statement(cur, ind+4);
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}
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fprintf(out, "%*send\n", ind, "");
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break;
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}
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case IVL_ST_CONDIT: {
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ivl_statement_t t = ivl_stmt_cond_true(net);
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ivl_statement_t f = ivl_stmt_cond_false(net);
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fprintf(out, "%*sif (", ind, "");
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show_expression(ivl_stmt_cond_expr(net));
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fprintf(out, ")\n");
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if (t)
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show_statement(t, ind+4);
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else
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fprintf(out, "%*s;\n", ind+4, "");
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if (f) {
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fprintf(out, "%*selse\n", ind, "");
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show_statement(f, ind+4);
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}
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break;
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}
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case IVL_ST_DELAY:
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fprintf(out, "%*s#%lu\n", ind, "", ivl_stmt_delay_val(net));
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show_statement(ivl_stmt_sub_stmt(net), ind+2);
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break;
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case IVL_ST_NOOP:
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fprintf(out, "%*s/* noop */;\n", ind, "");
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break;
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case IVL_ST_STASK:
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if (ivl_stmt_parm_count(net) == 0) {
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fprintf(out, "%*s%s;\n", ind, "", ivl_stmt_name(net));
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} else {
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unsigned idx;
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fprintf(out, "%*s%s(", ind, "", ivl_stmt_name(net));
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show_expression(ivl_stmt_parm(net, 0));
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for (idx = 1 ; idx < ivl_stmt_parm_count(net) ; idx += 1) {
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fprintf(out, ", ");
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show_expression(ivl_stmt_parm(net, idx));
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}
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fprintf(out, ");\n");
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}
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break;
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case IVL_ST_WAIT:
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fprintf(out, "%*s@(...)\n", ind, "");
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show_statement(ivl_stmt_sub_stmt(net), ind+2);
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break;
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case IVL_ST_WHILE:
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fprintf(out, "%*swhile (<?>)\n", ind, "");
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show_statement(ivl_stmt_sub_stmt(net), ind+2);
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break;
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default:
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fprintf(out, "%*sunknown statement type (%u)\n", ind, "", code);
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}
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}
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/*
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* Processes are all collected by ivl and I draw them here in the root
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* scope. This way, I don't need to do anything about scope
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* references.
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*/
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static int show_process(ivl_process_t net, void*x)
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{
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switch (ivl_process_type(net)) {
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case IVL_PR_INITIAL:
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fprintf(out, " initial\n");
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break;
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case IVL_PR_ALWAYS:
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fprintf(out, " always\n");
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break;
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case IVL_PR_FINAL:
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fprintf(out, " final\n");
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break;
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}
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show_statement(ivl_process_stmt(net), 8);
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return 0;
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}
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int target_design(ivl_design_t des)
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{
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const char*path = ivl_design_flag(des, "-o");
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if (path == 0) {
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return -1;
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}
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out = fopen(path, "w");
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if (out == 0) {
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perror(path);
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return -2;
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}
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fprintf(out, "module %s;\n", ivl_scope_name(ivl_design_root(des)));
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/* Declare all the signals. */
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draw_scoped_objects(des);
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/* Declare logic gates. */
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draw_scope_logic(ivl_design_root(des), 0);
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/* Write out processes. */
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ivl_design_process(des, show_process, 0);
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fprintf(out, "endmodule\n");
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fclose(out);
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return 0;
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}
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/*
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* $Log: verilog.c,v $
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* Revision 1.29 2007/02/26 19:49:50 steve
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* Spelling fixes (larry doolittle)
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*
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* Revision 1.28 2004/02/15 18:03:30 steve
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* Cleanup of warnings.
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*
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* Revision 1.27 2002/08/12 01:35:03 steve
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* conditional ident string using autoconfig.
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*
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* Revision 1.26 2001/12/15 02:13:17 steve
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* The IVL_SIT_WIRE type does not exist, it is a
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* synonym for IVL_SIT_TRI.
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*
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* Revision 1.25 2001/09/30 16:45:10 steve
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* Fix some Cygwin DLL handling. (Venkat Iyer)
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*
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* Revision 1.24 2001/07/25 03:10:50 steve
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* Create a config.h.in file to hold all the config
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* junk, and support gcc 3.0. (Stephan Boettcher)
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*
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* Revision 1.23 2001/05/22 02:14:47 steve
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* Update the mingw build to not require cygwin files.
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*
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* Revision 1.22 2001/05/20 15:09:40 steve
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* Mingw32 support (Venkat Iyer)
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*
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* Revision 1.21 2001/05/08 23:59:33 steve
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* Add ivl and vvp.tgt support for memories in
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* expressions and l-values. (Stephan Boettcher)
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*
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* Revision 1.20 2001/02/07 22:22:00 steve
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* ivl_target header search path fixes.
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*
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* Revision 1.19 2001/01/15 00:05:39 steve
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* Add client data pointer for scope and process scanners.
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*
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* Revision 1.18 2000/11/09 05:14:07 steve
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* show concatenation operators.
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*
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* Revision 1.17 2000/11/07 06:14:06 steve
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* Display l-values with width.
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*
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* Revision 1.16 2000/10/26 16:42:25 steve
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* draw proper signal references for the gates.
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*
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* Revision 1.15 2000/10/26 00:32:28 steve
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* emit declarations of signals and gates.
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*
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* Revision 1.14 2000/10/25 05:41:55 steve
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* Scan the processes, and get the target signals
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*
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* Revision 1.13 2000/10/21 16:49:45 steve
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* Reduce the target entry points to the target_design.
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*
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* Revision 1.12 2000/10/15 21:02:09 steve
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* Makefile patches to support target loading under cygwin.
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*
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* Revision 1.11 2000/10/15 04:46:23 steve
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* Scopes and processes are accessible randomly from
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* the design, and signals and logic are accessible
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* from scopes. Remove the target calls that are no
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* longer needed.
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*
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* Add the ivl_nexus_ptr_t and the means to get at
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* them from nexus objects.
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*
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* Give names to methods that manipulate the ivl_design_t
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* type more consistent names.
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*/
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